AMD Roadmap for Coming Year and Beyond

nexex writes: "With a new year comes new products, and AMD certainly has some new toys for us to drool over. The first of 2002 will see the release of "Thoroughbred," a version of the Athlon XP chip made on the more advanced 130-nanometer manufacturing process. The chip will cover 80 square millimeters in area, or 65 percent of the space of the "Northwood" Pentium 4 coming from Intel in early January. That chip measures 116 square millimeters, according to AMD estimates. For more, including info on Clawhammer, Sledgehammer, and all the Intel bashing you can handle, see here." I hope they don't really mean that "these new chips will also consume less heat than current AMD notebooks chips."

Comments

Technical information on Thoroughbred

[Black Acid]

Geek.com has a short but informative page on AMD's future Thoroughbred processor. Interestingly, AMD will produce both mobile and desktop versions of the processor. Some specifics:

Speed: 2.0GHz?
Bus Speed: 133*2=266
L1 Cache: 128K
L2 Cache: 256K
Microns: .13=130nm
Form Factor: Socket A

Link to 'official' roadmap

[Zach`]

http://www.amd.com/us-en/Corporate/VirtualPressRoo m/0,,51_104_608,00.html

That link includes a pretty roadmap graphic. It also shows the Barton design following the Thoroughbred release.

Silicon-on-Insulator (SOI) technology

[Black Acid]

The article says AMD's new processor will utilize SOI technology. A great page on SOI technology is UCL/DICE - SOI (Silicon On Insulator) and quantum devices. Heavy stuff. There's also a nice explaination of SOI from IBM:

SOI refers to placing a thin layer of silicon on top of an insulator, such as silicon oxide or glass. The transistors (switches that are used in microprocessors) are then built on top of this thin layer of SOI. The basic idea is that the SOI layer reduces the capacitance of the switch, so it operates faster.

IBM has built and tested SOI-based chips that have 20-35 percent (frequency) performance gain or 2-3X lower power at the same frequency as bulk CMOS technology. This is equivalent to about two years of progress in bulk CMOS technology.

The ultimate goal is to use SOI as the substrate for mainstream CMOS technology used in the manufacturing of microprocessor chips that power computers and other emerging electronic devices.

Earthweb has a detailed explaination of SOI by Robert Richmond. Apparently, SOI was invented by IBM.

Re:Silicon-on-Insulator (SOI) technology

[Harumuka]

Indeed. IBM's new technology however will likely become widespread in the near future. AMD's processor will no doubt increase interest in SOI, and prove it's an effective solution. Already Samsung's upcoming 64-bit 21264E Compaq Alpha is rumored to have SOI.

SOI is the wave of the future. In the next 4-5 years, IBM hopes to push processor speeds to 5GHz.

Re:What keeps Intel alive?

[Metrol]

If the decisions were made on a strict technical basis, what would keep Intel alive?

Lower cost bundling to the OEM's
Fewer customer returns
Faster turn around to OEM's with replacement parts
High power processors ready for laptops today

Mind you, I run 2 Athlon machines at home, and 1 at work. On all of these machines I have been extremely pleased with stability and performance of the AMD processors. I always build my own PC's, and I am not an OEM. I don't have the same kinds of concerns they do.

Mabye the free market rules are not applied to computers?

The free market works just peachy. Athlons are doing quite well with folks such as myself purchasing individual components. It's the OEM space that AMD is hurting in, and for a variety of reasons.

Itanium architecture vs. the mainstream

[Animats]

Even within Intel, there was considerable opposition to the Itanium. Very Long Instruction Word machines are notoriously hard to program, and take very elaborate compilers to get even marginally good utilization of their explicit parallelism.

The best case for VLIW (Intel calls it EPIC, because VLIW has a bad rep, but it's VLIW) is inner number-crunching loops. Think rendering, audio/video compression and decompression, and similar stuff. But most computing isn't about tightly coded inner loops any more. Least of all on servers. Mostly, it's about calling lots of little subroutines that call more little subroutines. That's the worst case for explicit parallelism. Unless the compiler optimizes over subroutine call boundaries (which typically means very heavy inlining), explicit concurrency stalls at each subroutine call. Not good. The HP compiler guys working on the Itanium compiler admitted a few years back that it was going to take a major breakthrough to generate good Itanium code.

Three times in the past, Intel has tried to move away from the x86 architecture to a new, more modern one. The iAPX 432, the i860, and the i960 were all moves in that direction. All three were dismal flops. In Andy Grove's book, Only the Paranoid Survive, he takes this as a lesson that Intel should't try to force an architecture change on its customers.

I would have expected Intel to come up with the Sledgehammer and somebody else to be pushing the Itanium.