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Scientific American on 3-D Chips
m5shiv writes: "Scientific American is running a feature on 3-D Memory Chips. These devices look like they will significantly reduce the cost of PDA's and other handheld devices as well as replacing analog film.
By stacking devices vertically, density goes up considerably. The company,
Matrix Semiconductor, appears to have some very interesting investors such as Kodak, Sony
and Microsoft."
The article talked about how heat dissipation will be impaired by the 3-D structure (obviously, when you increase volume relative to surface area.) Maybe in years to come we'll see some sort of chip/heatsink integration to channel heat directly from the interior of the 3d structure to the outside by the heatsink rather than the normal dissipation through the chip.
If you read the bottom of the article, you notice the author holds 14 patents for this new technology.
Good job they finally invented these. I kept losing my 1 and 2-dimensional memory chips down the back of the couch.
www.onlinescam.com - May contain nuts
No its called venture capital. Anytime you are making money, there becomes a need to spend it. This is a good way for big companies to spend all that cash they are generating. It does look good that they are stimulating new startups, however I am quite sure they expect a return on their investment.
...I thought it was some kind of gimmick on SciAm's part that allowed us to read their magazines in 3D if we had a decent 3D card... heh... kinda like their April Fool's articles.
"Backups are for wimps. Real men upload their data to an FTP site and have everyone else mirror it." -- Linus Torvalds
Matrix 3-D Memory is a field-programmable, archival medium. Cards with 3DM are write-once and the programming can happen all at once or in parts over time. Once on the card, the data is secure for generations and can be read repeatedly.
So it's merely a writable-CD-on-a-chip. Maybe they will develop a rewritable version someday :-)
Omnis basim vester nobis compete sunt.
Having been postponed or negated several times now, should we call Moore's law a postulation at best?
At first reading this technology seems like it has a future, in that, sure it's early in its infancy, but somebody will come along and make it work.
But what we're really talking about is not 3-D, it's just stacked 2-D. In fact technically, all computer chips are 1-D.
Because of the limitation of the fact that the Silicon crystal needs to be monolithic, that is, a lattice of atoms completely ordered throughout the chip we've got to think outside the box, this guy's inside the box, but realistically, this is to save money, and he wants to see something before his great grand kids are born.
The heart of the problem is the crystal flat surface. What we need is a crystal that grows out and up in such as manner as to be a monolithic latice but also compartmentalized. A cube, with little windows and rooms and holes so that the dope can get in.
Completely revolutionized fabrication thinking. We'll see it in less than 50 years.
It doesn't seem to be discussed in this article, but there is much progress being made on "3D copiers," computerized machines that will build complicated 3-dimensional objects one layer at a time out of ice or plastics. Because of how these objects are constructed, shapes that would be impossible to carve from a solid mass can be "molded" from the bottom up or from the inside-out.
If 3D chip design proliferates, I predict that these two technologies will eventually merge. Sophisticated chips will be assembled one layer at a time, perhaps one layer of atoms at a time, with electronic pathways twisting and turning through a three-dimensional block of material designed to ferry heat away from the core of the device. The main advantage, of course, would be enabling shorter pathways from one part of the chip to another, improving further as design improves. Perhaps in time motherboards would be replaced by "motherblocks" and the entire computer will become far more portable.
about the article in my opinion was the part saying that we are nearing the limit of miniaturisation of electronic components.
I mean, think about it.
If we're going to reach the limit of how small we can make these transistors by say 2020 (by which time we'll most likely be up to around 30Ghz processors), that's a major limitation in this industry.
The way I see it, it could go one of two ways:
1. We reach an inescapable limit of electronics, and the entire computer semiconductor industry implodes because it can't keep up with it's own reputation for performance increases.
2. Before that deadline occurs, some new fantastic and mindblowing technology is created. By this I don't mean some 'chip-stacking-bastardisation' of electronics but some true breakthrough.
Whichever way it goes, it's going to be very exciting, and I'm glad I'll be around to see it. Considering how much our lives are impacted by electronics these days, it could be the modern-day equivalent of the industrial revolution.
The first products incorporating such 3-D microchips--memory cards cheap enough to use as digital film and audio-recording media--are scheduled to appear later this year.
... They've got to hurry. There's only 20 days left...
This initial size doesn't bother me. As it's perfected and costs go down that would grow fast enough. Being WORM media is another issue though. I understand that this is a stepping stone to dynamic media, but at the moment I can get CD-Rs for around $.50/unit that are a proven media, hold much more data, and are already widely supported. And guess what: there are CD-RW already too (he can't do that yet). The heat thing could also be/not be an issue. Perhaps since it's stacked vert it will cool better. It's certainly harder to cover all surfaces in 3D. I have this vision of a cube with a heatsink on it's five exposed sides, only to have a core meltdown.
I'm against picketing, but I don't know how to show it.
Just for the non-article-reading record, the application towards "digital film" is only that they expect to make really really dense memory devices, so what this technology may replace is CF, not chemical/"analog" film, or even its digital equivalent, like CCD's.
-- Watch the REAL Jon Katz.
This technology looks interesting but there is definitely a good share of hype in both the SciAm article and the company's web site.
In particular, there is a suggestion that there are cost savings in part because the surface area of a "3d chip" is less than "1d chips" since 1d chips have more surface area there is a greater chance a defect will happen within that area. (Thus "small yield.") This is a spurious suggestion for the following reasons:
1. Each layer of the "3d" chip is subject to abnormality risk. (Thus real risk is LAYERS x AREA x RISK. For 1d chip AREA is bigger, but LAYERS = 1.)
2. The chip is mechanically "ground flat" after each layer to prepare for the next. I'm sure this works and I am also sure there a failure rate greater than zero for this operation.
3. Perfect alignment of the layers is required otherwise one of more parts of the "cube" will fail. They are working on fault tollerance issues right now, and they should.
Bottom line is that every bad chip drives up the final production cost. This is true for 1d and 3d. Seems like all the risks of 1d apply to 3d and now there are a few more. How will this be cheaper in the short run?
Let's not get into the heat issue that has not been resolved.
I hope they succeed, but the oversimplifications made trying to sell this thing bug me.
--- -- - -
Give me LIBERTY, or give me a check.
Modest, he's not.
The problem, as someone else pointed out, is yield. This involves running the chip through all the steps of lithography, deposition, and etching many times, usually losing a few devices to process flaws on each pass.
That's why this guy talks about needing redundancy and error recovery. That's nothing new; as far back as the 1970s, chips have been designed with redundant parts that were bypassed during tests, like bad spots on disk. This works well for memory, badly for more complex logic. Historically, the semiconductor industry has considered redundancy, but the wafer fab people always got the yields up to where it wasn't necessary.
It's clear that this will make memories smaller, but not necessarily cheaper. The number of fab steps per bit fabricated is equal or higher, not lower. Yes, there's a savings on the raw silicon, but that's not a big fraction of chip cost.
There's also the fact that RAM doesn't take up a significant volume in most current products. Maybe 1% of a PC's case volume is RAM chips. This guy is thinking not of PCs, but portable applications, which is probably right. There's also more price headroom on things like "memory sticks" and "flash cards" than on commodity RAM for computers.
Notice that he's also thinking of slow, low-duty-cycle applications, like storing music and video. That cuts the heat dissipation. Cooling the gates in the middle layers will be tough.
That's what I first thought, until I read further into the article. This is NOT a stack of IC's. It's a process for growing more layers of transistors on the surface of one IC. Theoretically, it should cost less than stacked IC's, and may eventually cost less than a set of "2D" (that is, single transistor layer) chips to be soldered onto a board side by side. (A significant part of the cost of a typical memory IC is in attaching the leads for the outside world, covering it in epoxy, and placing it on a board.) However, the cost savings depend on the percentage of finished chips that pass test; if you've cut the raw cost by 50% but cut the yield by 75%, then the cost per working chip is higher. The article doesn't say anything about yields, but if they are actually shipping production quantities for digital cameras, they probably doing fairly well at solving the yield issues, and will do better soon...
A digital camera is one application where density may count more than price, and I don't see how the Matrix chips can be beat for density. In conventional IC's, most of the silicon is below the active areas and only provides mechanical support. Stack those IC's, and you have many layers of non-functional silicon. The Matrix chip has just one.
Stacked chips have limited vertical interconnects -- either you connect them only at the edges, or you drill holes through the chips (much bigger than other IC fixtures) and metal-plate those as vertical wires. The Matrix chips can have true 3D interconnects, at the size of other IC features. This may not mean much to a plain memory chip, but it could be very important to other applications...