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Intel Looks to Billion-Transistor Processors
Weedstock writes: "EE Times has an article about Intel's next decade roadmap. It explains what are the current issues with the actual "plastic bumped organic land grid array" packaging technology and how it will be modified into a "bumpless package with built-up layers" to accomodate billion-transistor processors."
http://www.anandtech.com/showdoc.html?i=1542 If the URL is bad. Go to www.anandtech.com, CPU on the right side, and look under recent articles for the BBUL story.
This was more or less just a summary article. You had to be somewhat familiar with a number of announcements Intel made over the last year to get any sense of importance out of this.
Bumped to bumpless is important because the solder balls were starting to dominate layout and packaging considerations.
Having better lithography processes and smaller traces is important because even though everyone expects them to continue to improve, someone still has to discover the technology required to do so first.
The new gate oxide has been shown off and does exist. It's only really improvement is for current leakage so it's not stop the world kind of news. Cost per wafer and manufacturability with existing machinery are the real things to worry about.
This is a different SOI approach than previous chipmakers have been using. They're also doing variations of xOI whereas other approaches use a standard silicon substrate.
The whole slashdot crew needs to learn more than just technology before posting articles.
By "embed" they mean "stick the core into a hole so that the top of the core is level with the surface of the packaging".
In other words, your heatsink will have more or less direct contact with the core, but there will be other material around which will make sure that you don't accidentally crush the core when you push down on the heatsink.
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Firstly they did mention reducing gate leakage current by a factor of 3 i believe which means the chip will produce a lot less heat.
As for embedding the core in the packaging - it's probably a great bonus. As has been pointed out this means that the top of your chip will be completely flush so you'll hopefully get better thermal transfer since you have a bigger surface area.
On a current intel chip the space between the packaging and the heatsink is currently acting as an insulator (since air does that best when it's not moving).
In addition to this, I would speculate that if the core is embedded into the packaging it might allow for small heat pipes to run directly into the core, allowing particularly hot areas of the chip to have additional passive cooling.
That said, given fabrication facilities i'd struggle to make even a single pnp transistor and whilst i could probably remember how to build simple mos (and hence cmos) gates - i'd struggle to replicate what intel was doing in the 70s... so dont take me as any sort of authority on this one.