Intel's Big Chip

DeadBugs writes "News.com has an article about the size of the upcoming revision for the Itanium. The "McKinley" chip will be 464 square millimeters which would make it one of the largest ever produced. Most of this is due to the 64 bit registers and 3MB of Level 3 Cache. There is also a link to an article about "Chivano" an Itanium which will include concepts from the Alpha architecture"

Comments

Wow!

[JoeLinux]

Intel gets it right! Morce_Cache==Good_Thing. Was anyone else scratching their head over the 8k of level 1 cache on the Pentium 4?

Joe

big chip... big fan

[Transient0]

i wonder if the oversized chip will lead to particular cooling difficulties(i.e. standard fans and heatsinks can't cool the entire surface area)...

Re:big chip... big fan

[m4g02]

Not really, that would apply if the heatsink became biger while the chip keeped the same size, its like 1 (common chip size) - 1 (heatsink size) is 0, while 2 (new chip size) - 2 (heatsink size) also is 0, i guess the porblem isnt the heat but the backwards compatibility with other accessories... what isnt really like a porblem.

Re:big chip... big fan

[Sokie]

But if you have drastic enough temperature deltas in the die itself to make this appreciable, then there is no heatsink design that is going to be precise enough to effectively combat those hot spots. Basically you have to design your heatsink to cool the hottest part of the chip to acceptable levels. Increasing the surface area of the die (without increasing the amount of total heat output) will lower (however slightly) the highest temperature spot on the die, making it (again however slightly) easier to cool.

Also, there is going to be horizontal thermal dissapation regardless of the thermal resistance of the materials involved. If I have a die that generates 1W of heat in a 200 mm^2 area, even if it is not generated uniformly, and I then increase the area to 300 mm^2 with the same total heat output value, that extra area IS going to be heated, probably substantially, regardless of whether it is generating it's own heat. That means that the overall average temperature has to go down somewhere.

The points you make are however perfectly valid and relevant, but the point of the original poster was supposing that it would be larger surface area of the die that would make it harder to cool, not any new thermal hotspots. I was simply saying that there aren't many ways that increasing the surface area can make something harder to cool.

Humm... aren't they a bit late?

[RinkSpringer]

Sounds neato to me, but since Dual XP's and such are also starting to get very acceptable pricing around now...

Sure, 64 bit is nice... but a good multiprocessor solution might do wonders too.

Then again, I may be missing the point.. but if a company can get a Dual XP or Dual P4 for less, they would probably go for that... Oracle and such is probably already optimized for such configurations... and since XP's and P4's have a good reputation (eg reliable), it might give them more confidence.

Somehow, I just don't think this would be such a big profit hit for them.

Re:Humm... aren't they a bit late?

[ocelotbob]

You're missing the market. These chips, at least until they get them up to X86 speeds, aren't going to be used very much in the workstation market. These chips are going to be used in such places as database servers, where the current hack of 36 bit addressing used in Intel's current high end chips, the Xenons, is starting to fall apart. 64 bits doesn't mean much performance wise - in some applications, it's slower than 32 bits, but it means a world of difference when talking about storage. Instead of having hacks to get around the 4 gig barrier, one could, in theory at least, keep an entire database in memory.

A few minor points

[mtnharo]

Just for some minor clarifications: The 464 mm squared is the area of the actual cpu die. Like the little square on top of an athlon. So 2 cm per side die is kind of huge for a processor. The actual processor out of the box would have to be much larger than previous models. Next, 3 MB cache sounds nice, but L3? It may be on die, but by that point the clock reduction probably makes it perform equivalently to a 256 k L1 cache, or a 512 or larger L2. Not that it won't help a lot for complicated instructions, and it's probably less expensive/difficult to engineer to hook a larger amount of cache to a slower pipeline than to add more cache deeper into the cpu's core. 64-bit cpu's will be important in the future, but only when compatible apps and OS designs become mainstream.

Itanium at 1.6 GHz in 2003 ?

[Utopia]

For the article
Madison is expected to come out in 2003 and run between 1.2GHz and 1.6GHz, according to sources.

I wonder how Intel expects people to adopt Itanium-based processors considering
that x86 processors will be running at 4GHz in 2003.

Who cares about GHz...

[jbf]

... if you can't run the apps.

Intel x86 is restricted to 48-bit addressing (with segment registers), and practically 64GB with modern OSes. (http://linux-mm.org/)

If I want more than 64GB of addressable physical memory (which I do for some apps), then who cares if you can give me a 32-bit x86 running at 900GHz, it's not going to do diddly squat for me, since _going over the PCI bus_ for swap is going to kill me vs a 1.6GHz 64-bit processor. And since you need to go over the PCI bus just to get to a pseudo-disk stuffed with RAM, that solution is still bogus.

I see your point that this isn't what Joe Blow's gonna put on his desk. But the improved address space is definately a big win, and that's assuming that they can't ramp up the clock speed in a hurry.

Re:Large?

[max cohen]

The deal is this: larger die size chips are harder manufacture cost-effectively make because you get fewer good die per wafer. A wafer is a fixed size and costs the same to process, regardless of the number of functional die you actually get from it. So, the more die you fit on it, and the more die that actually work when you are finished processing, the lower your final selling price can be. Since the die size for this chip is much larger than "normal" and will be made in fabs that arguably will have the same defectivity rates, they will likely get less working die from a wafer than "normal" and thus their costs to the consumer will be larger.

NOT wow!

[Anonymous Coward]

More cache = larger die size = low yeild per wafer = very expensive processors = fewer sales.

This giant die is going to be very hard to produce in any quantity. CPU makers must balance acceptable cache levels with acceptable production costs.