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Hope for MIPS, From Toshiba
CDWert writes: "EE Times is reporting MIPS is teaming up with Toshiba, to develop their next generation 64 bit proccesor. After all the Itanium Speak and X86-64 talk going on here and the premature predictions of MIPS demise, through their inability to fund the next round I thought this would be refresing to MIPS fans." According to the article though, there will be no product until at least a year from now.
Read the first two paragraphs of the story. Toshiba is taking MIPS' Amethyst core and developing an embedded controller around it, to be known as TX99. With 600MHz clock, scalable to 1GHz, this is great news for the embedded world and will position MIPS as a competitor to Motorolla for embedded h/w. But it isn't really a new chip for MIPS, just a variation on an existing one.
Also, the purchasers of commodity embedded processors tend to be slow to change, so MIPS/Toshiba will have to make a compelling case to do so.
The clearance system sounds logical. It is not. It is completely arbitrary. -- John Bolton
To anyone who's coded in Assembly, MIPS is pure beauty.
The entire ISA is minimized so as to accomplish most operations in the fewest clock ticks (duh -- it's RISC). But after dealing with the crappy x86 design, it is so refreshing to deal with a logical and straightforward architecture such as MIPS. No messing with ES or DS pointers, just simple, general purpose registers. And don't get me started on the "extended" register size kludge in x86 (EAX -- what the hell?). MIPS doesn't have such baggage.
I've coded for SPARCs, I coded for Motorola's 68k and 68HC processors. But nothing beats MIPS in terms of power from simplicity.
Itanium will finally get a 64-bit competitor?
</sarcasm>
Seriously, the way some people write about the Itanium, you would think nobody had every created a 64-bits processor before.
> So, please tell me where does one need 1 GHz embedded processors?
Embedded systems are getting quite fancy nowadays; it was claimed in "Embedded Systems Programming," January 2002, that cell phones have 10^6 lines of C or C++. They need the horsepower.
For example, it might be more cost-effective to implement signal processing in a fast microcontroller, than to have a DSP chip and a general-purpose microcontroller.
The clearance system sounds logical. It is not. It is completely arbitrary. -- John Bolton
I love reading the comments that say things like, "MIPS will revolutionize the embedded market!" and "Maybe there's hope for SGI yet!"
MIPS microprocessors are everywhere, and have been for years and years. They're in your TV, your cell phone, your microwave oven. They're in those cool little GPS receivers that everybody wants for Christmas. They're in the PlayStation 2, Replay TV PVRs, and most of Cisco's routers.
Look around your office. There are probably half a dozen MIPS processors within about twenty feet of you right now.
This is nothing new or revolutionary, and it has nothing to do with the MIPS R10K, R12K, and R14K processors that SGI uses in their computers. Everybody calm down.
The number of cache lines you get in your caches isn't necessarily connected with whether your CPU is a 32-bit or 64-bit CPU; cache lines are typically bigger than the word size of the processor, and not necessarily governed by the word size of the processor.
If you have 64-bit pointers or integers, your variables may take a larger fraction of a cache line, though, so that you get more cache misses and have to go back to memory more often.
You won't necessarily have 64-bit pointers just because your CPU is a 64-bit CPU, and you won't even necessarily have most or all integers be 64-bit. Compilers for 64-bit CPUs may still generate 32-bit code - except when you're processing 64-bit integral data types, in which case it may generate 64-bit code for those data items.