Hope for MIPS, From Toshiba
CDWert writes: "EE Times is reporting MIPS is teaming up with Toshiba, to develop their next generation 64 bit proccesor. After all the Itanium Speak and X86-64 talk going on here and the premature predictions of MIPS demise, through their inability to fund the next round I thought this would be refresing to MIPS fans." According to the article though, there will be no product until at least a year from now.
I don't know about others, but as for Microsoft, they're working on MIPS compilers.
What I found especially interesting was the range of devices that MIPS chips are used in. It occurred to me that very few people probably need a 2GHz P4 in their inkjet printers and mobile phones.
It'll be interesting to see how it compares to the SiByte SB1, which a MIPS64 instruction set SOC with two cores.
Well I never thought Id get an article posted, submitted 7 and never one got accepted, ANYWAY as a result, I didnt complete my story, Just figuring what the hell and let the slashdot editors take it and run with it.
One of the coolest parts, I thought it will be a 0.10 micron process, is anyone else using this small of a process yet ?
Is there hope for SGI and MIPS or has SGI decided against it in total ?
Sig went tro...aahemmm.....fishing........
If we're getting by pretty well on 32-bit chips, where's the market for 64-bit chips? High speed routers?
-cyc
/.'s 10 Millionth
ARM's stuff has gained massive ground in the mobile devices and virtually squeezed MIPS (and everyone else) out of that market entirely. The trouble is that MIPS are being squeezed on the upper end of the scale as well by some seriously grunty main CPUs which are starting to adopte the same sort of friendliness to bespoke licensing for incorporation into VLSIs. Such as IBM's PowerPC chips. By way of an example, Sony aren't going with MIPS for the PS3, they're teaming up with IBM.
So where is left for MIPS? Sounds like they're going after SoT type applications which are in need of serious performance, niche that they are. Make something all singing, all dancing with a damn nippy core in there and you hit applications which ARM haven't got the performance for and PPC type chips don't have the power considerations and SoT/integration levels for. Good luck to them.
I understand you confusion.
Your question has to be one of the most confusing Ive ever read, its valid and a good question, the answer is MIPS is far more experienced in RISC architecture than Intel, and second the low cost low power consupion goal from the beggining, they will be using a 0.10 process and any competition is good competition, this processor though is intended for imbedded devices, howd you like a 1ghz risc pda ? Cant really see you squeezing an Itaninum in.
I didnt mean to be terse about your question, It gave me a laugh I had to read it 3 times, kinda like how much wood would a woodchuk chuck if a woodchuck could chuck wood....:)
Sig went tro...aahemmm.....fishing........
Although Linux is ostensibly a competitor to Windows, it has made most of its inroads in the "big iron" market.
Most of the non-Intel processors are in this market (HP-RISC, SPARC, MIPS)-so what we are seeing is Linux, in effect, killing these other processors. High-end production houses are leaving their SGIs for custom build x86 boxes, servers are dropping Sun and IBM for x86 offerings from Dell and Compaq.
As Sun slowly fades into the night (no pun intended) the only non-x86 CPU with any installed base in the high-performance market anymore is the PowerPC, and its fate is closely tied to the shaky Apple, which is struggling to re-invent itself with OS X.
God bless Toshiba! I wonder if Sony would add some R&D into that pot in preparation for the PS3, and maybe we would have another high-performance chip to compete with Intel.
Liberate your mind in two clicks or less.
The ISA may be nice, but as anyone that has debugged real code will attest its not meant to be human readable. The problem comes from the MIPS idea of having the next instruction execute no matter what (with the exception of a few instructions which flush the pipeline). The result is that after a branch you execute the instruction immediately after it, then you execute the instruction at the branch. Apply this repeatedly, and you'll see the problem...ugh.
We recently took an SGI Octane 2 (current SGI state-of-the-art) and an IBM Intellistation with a FireGL3 card for a test drive. The SGI Octane 2 was a 400MHz MIPS R14000 chip, and the IBM a P6 @ 1.7 GHz.
The Intellistation is approximately a third the cost of an Octane 2. It also outperformed it by a factor of 2.5. It outperformed our older Octanes (R12000 @ 300MHz) by a factor of 3.5. Not just CPU (renderman & vmantra) but also interactive OpenGL. Same factor across the boards.
Unless MIPS can pull a serious rabbit out of their ass, they're far, far, far behind INTEL, no matter how you slice it.
I've done a bunch of those too amongst others, and my personal fave for "nicest ISA" is the ARC. Pretty much the nicest bits of MIPS mixed with the nicest bits of ARM.
What would Lemmy do?