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SuSE Submits Enhancements for AMD Hammer

Posted by ryuzaki0 on from the getting-the-features-in dept.

ackthpt writes "SuSE has this press release as they are submitting enhancements to the Linux kernal particular to the AMD's x86-64 processor instruction set. Anticipated for 2.6 kernel, some enhancements may appear in 2.4, as development is only beginning on 2.5. AMD's take on the announcement as well.". nik notes that SuSE join NetBSD in having ports to Hammer. Usenix members can see the paper Wasabi's Frank van der Linden wrote about the porting effort.

9 of 57 comments (clear)

  1. already being done... by scorcherer · · Score: 5, Informative

    Take a look at GCC main page and you'll see a note on the x86-64 port contributed by SuSE.

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  2. Re:But where/when can we get a Hammer? by Phosphor3k · · Score: 3, Informative

    They are tentatively shceduled to be released at the end of 2002. I would wager that they won't be available in force to the common man until sometime 1st quarter 2003.

  3. Re:Newbie 64-bit question by Flavio · · Score: 3, Informative

    This is called a SIMD (single instruction, multiple data) operation. It's what MMX is all about.

    It's usually not worth doing this if there's no SIMD hardware support, because the time wasted loading your values and then separating them isn't compensated by the gain in speed. Of course there are special cases (like when dealing with bit strings) where this is used by definition (and will be an improvement).

  4. Re:misleading headline by bears · · Score: 4, Informative

    According to one of the developers from SuSE who worked on this (and demoed SuSE running under one of the x86-64 simulators at a recent OxLUG talk ), SuSE and other porters did indeed make suggestions to AMD as to details of the architecture which were taken up by AMD.

  5. Re:Newbie 64-bit question by VAXman · · Score: 3, Informative

    No, you can't, unless you can guarantee that the result from the lower half of the operand will not affect any bits in the upper half. For multiplication this will happen all the time but for addition it will happen whenever the lower operand carries over.

    Besides, 64 bit operations are higher latency than 32 bit operations, and the cost of all of the shifting and masking to separate the results would be very high. It would be much faster to just do two separate 32 bit operations.

    SIMD is a different story since the hardware assembles and reassembled the operands, and executes them on separate executions units.

  6. Interesting read by Matrim9 · · Score: 4, Informative

    http://www6.tomshardware.com/cpu/02q1/020227/

    Interesting - they tested one of the Hammer CPUs on Suse, but they only ran XP in 32-bit... :o

    1. Re:Interesting read by Phosphor3k · · Score: 3, Informative

      Just a clarification. Tom did not test these. This was a demonstration at a trade show that everyone and their brother has been reporting on. No one was allowed to test any software on these machines. However, this is the FIRST batch of hammers tested in public. The series on the cpu was A0. Generally, AMD and Intel do not test/show of such early production CPUs to the public as they are still going through testing/debugging.

  7. Re:great, but what about GCC? by DrSkwid · · Score: 3, Informative

    Not necessarily. Recall from this slashdot story about this article the intel compiler also showed similar results over GCC when targetting the Athlon.

    GCC's mission statement is not the running time of executable code, we've recently been having a thread about it on the plan9 mailing list (or comp.os.plan9). (although ours started as a flame from Thomas Bushnell that plan9's 8c was nothing more than a "cute toy" - 8c is more concerned with compilation speed than execution time where it beats GCC hands down, if you want raw execution speed look elsewhere).

    It could well be that Intel's compiler will show similar performance gains over GCC on the Hammer.

    I wonder if every problem will start to look like a nail when the hammer claws it's way out of the AMD tool box.

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  8. Re:great, but what about GCC? by VAXman · · Score: 3, Informative

    Oh, I have no doubt that Intel's compiler will produce great 32 bit code on Hammer. Hammer is just a proliferation of K7 with 64 bit extensions, and AMD knows how to optimize their hardware for that compiler (they use it when submitting their SPEC scores).

    But Intel's C compiler won't generate 64 bit code, which means that AMD has to rely on GCC for 64 bit applications. So any performance advantage of 64 bit is more than nullified because there's not a decent compiler for it.