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AMD Targets Web Pad & PDA Processor Market
According to this
press release
and this article
from The Register
, AMD has leveraged the technology portfolio of recently acquired
Alchemy Semiconductor
to introduce an ultra-low-power processor designed for sub-PC applications.
The chip is based on the Alchemy Au1 core and features, among
other things, an integrated LCD controller and a pair of Secure Digital controllers.
http://www.alchemysemi.com/product_info/secure_da
grnbrg
That port was cancelled while I was working for Symbian. Sure, it's almost a year since I switched employer, but I haven't heard anything about a new port since ... ;)
it's in my head
It actually runs linux, check on Montavista's site... they have the Linux LSP available for download for Alchemy's (sorry... AMD) au1000 which is the ancestor (just no lcd/sd controller, a little more power hungry) of the au1100. But you'd rather use Alchemy's au1500 which has a pci bus controller i guess...
well yes it is because the Pentium ISA is supposed to be obsolete.
.NET JIT's for ARM x86 IA64 and MIPS 32 Plus MIPS64
no one in their right mind would have predicted Intel or AMD would keep it going this long.
(they want to kill it witness IA64)
MIPS was actually designed for high performace useing a combination of compiler design and Hardware design it was a academic project and they got it right.
ARM was designed to be simple take up as little space as possible for manufacturing and implementation (only 2 engineers did the work to start with) as a by product it means that now with moores law you have a product that burns very little power
there are snags MIPS is more complicated than ARM but once you are over 100 MHz it pays dividends the amount of effort that Digital had to go through to do the StrongARM showed this and again with the StrongARM2 (Intel calls it the Xscale or PX250)
the StrongARM design team did not really like the idea of working for Intel so they went off and created Alchemy and got a 500Mhz part with not much trouble they also stuck on 2 10/100Net ports USB client and Host I2C and serial a pretty nice chip but funding took a hit and they went looking for investors AMD saw the money that Intel was making of StrongARM and thought that little Alchemy was a winner.
once AMD was on board they put a LCD contoller dumped 1 of the 2 network interfaces and bingo you have a better StrongARM than Xscale.
in terms of tools
what do you have on x86 ?
gcc intel and lcc (plus globs of half baked assemblers)
or ARM has: gcc, ARMCC, Greenhills and acorn
compared to MIPS : gcc algor sgi (plus lots of academic compilers)
oh and MS has
java has about the same but with sparc and some hardware implementations
regards
john jones
p.s. did I mention that MIPS is really the ONLY Volume 64bit RISC left after Intel butchery
Just FWIW, here's a couple processor heat numbers:
Desktop AMD AthlonXP 2000+ : 70.0W Max/62.0W typ
Desktop Intel P4 2.0GHz : 75.3W TDP
Desktop Intel P4 2.0A : 52.4W TDP
Mobile AMD Athlon4 1500+ : 25.0W TDP
Mobile Intel P4-M 1.6GHz : 30.0W TDP
Mobile Intel PIII-M 1.2GHz : 22.0W TDP
AMD Alchemy Au1100 400MHz : 0.25W Max
Intel XScale PX250 400MHz : 0.30W Max
Max = Maximum possible real-world power consumed by the chip
Typ = Typical power use under heavy processing
TDP = Thermal Design Power, usually just slightly higher then typical power, though it's defined by the manufacturer
So, just to keep things in perspective, we're talking about these embedded chips using two orders of magnitude less power then even laptop x86 chips. Now, obviously the performance isn't going to be at all the same, but in terms of power, it doesn't make any sense at all to compare the power consumption of either.
Ohh, and just for fun, here's one more chip:
Intel Intanium 800MHz : 130W Max
Regards
Tony
I realize that ARM is called a RISC instruction set, and has all the RISC goodness: load/store instructions, 3-operand arithmetic, simple decode, simple operations, and (almost) a flat register file. However, unlike "classic" RISC instruction sets, it has multiple instruction sizes, and therefore achieves noticably better code density.