Intel Shows Off 'Banias' Chip for Mobile Devices
deano writes "Intel has unveiled the first prototypes of their latest mobile "Banias" processors. The article states Banias systems with the Intel Odem Chipset will come out early 2003 and feature 802.11b. The article also speaks of the new Itanium with a 6Mb cache!"
... that the Intel Roadmap has been displaced -1.5 yrs. The 6 MB cache Itanic will be at least 18 months late. So sad - the chip has so much potential despite it's bad press. I've had a Sitka 450 2MB cache server for 3 years and its got to be the best Intel product ever made.
Do you want to remove linux?
Banias, formerly Caesarea Philippi, is the Arabic name for the Hellenistic city of Paneas whose name derives from Pan, the Greek god of herds and shepherds. His cult was observed in a large cave at the foot of Mount Hermon, where a source of the River Jordan emerges.
Pepperdine University has conducted digs in the area that have unearthed parts of a palace from Herod Agrippa II. Modern-day Banias is located in Israel, where the Intel design team for the new chip is based. The company typically code-names its chips after geographical features.
For reference, Banias is the name of a river in northern Israel - one of the three sources of the river Jordan. It's a pretty area, and great for gentle hiking. There are nice pictures of it here, here, here and through Google image search
Paranoia isn't an infectious condition, it's a way of life
The Banias is a small river in northern Israel, which feeds the Jordan river. And Odem means "ruby". They're just continuing their "name everything after running water" trend.
6 MB cache? The UltraSparc III has an 8 MB cache. Intel is still playing catch-up.
The UltraSparc III has off-die L3 cache. The Intel chip would be on-die.
Off-die L3 cache isn't too hard to do, and it's significantly slower.
6,000,000 bytes
* 8 bits to a byte
* 6 transistors to a bit
= 288 million transistors on its own
Add on the 1MB L2 (48 million transistors) and there you have the majority of the transistors in Madison (Avenue) processor. And the L2 cache is most likely has more than 6 transistors to a bit of storage, and so on - 450 million of the 500 million transistors are most likely for cache or cache control in the end.
Sure it can hurt. If increasing the size of the cache causes your access time to increase, then it can hurt very badly, because you're overall latency could increase if the benefit from a lower miss rate if offset by the higher hit time. Although it's true that the latency of second and third level caches affect performance much less than the first level.
Cache size is one of the most misleading processor benchmarks, more misleading than frequency, yet big caches command huge price premiums.