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The End Of The Innovation Road for CMOS
Elledan writes "According to this EE Times article, CMOS technology (also used to create CPUs with) is getting near the moment when we will no longer be able to create smaller structures with it. With the date for this moment set around 2012 and with no replacement technology in sight, this issue might become a real problem in the near future, as the article explains."
Yet it's a simple fact, that earth's oil reserves ARE limited and that exponential growth (or shrinkage) IS impossible in our limited universe. Pretending otherwise is just ignorance. With computers, it's not really a problem since nothing really crucially depends on getting more powerful computers all the time. Unfortunately, this is not so with fossil fuel reserves. Unless we find alternative energy sources, mankind is in really deep shit quite soon, not when fossil fuels run out, but well before that time, when they become much more expensive to get out of the ground. Realize that the comfortable predictions of 100 years or more of oil reserves include ones that will be 10 times more expensive to use.
The illegal we do immediately. The unconstitutional takes a little longer.
--Henry Kissinger
But even the article repeatedly says that the mask cost issue is a problem for the little guys, not the large ones like Intel. They can and will cheerfully swallow $600k respin costs, and more, to tapeout a successful new processor. So this aspect won't hurt processor development at all.
As for the CMOS scaling issue, the processor companies- i.e. Intel and AMD, have the pockets AND the incentive to find work-arounds. I promise you all that processors will continue to advance well beyond the year 2012. It may not be CMOS, and it may not be pretty :-), but it will work.
So for all of you who posted asking "what will we do when processors no longer advance", let me set your mind at ease- THAT won't happen for a long while yet.
Finally, while the subject of my post is "the end of processor advancement", I'll say a few words regarding other types of chips. I work as a hardware engineer for an ASIC house, and we produce at TSMC using the 0.18u process. The point is, that for our chips there is NO incentive to go to 0.13u or below. Nor will there be a reason for quite a while. The same is more or less true for MANY MANY other ASIC companies. So while the cutting edge- processors, Flash and graphic-chips companies will probably need to switch from CMOS to some other technology around 2012, that will in no way spell the end of CMOS, not for a VERY large segment of the ASICs market, and not for a VERY long time.
I think oil prediction is now on 40 years. It were 50 years 15 years ago. Okay it isn't that accurate but oil is decreasing. I'm 24 years old, and I estimate that I'll see the beginnings of the end of oil. There will be huge wars for the few remaining resources, I will tell you.
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Karma 50, and all I got was this lousy T-Shirt.
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I work in research at a university, and my PhD project is going to help solve this problem (and others) long before 2012. I can't get into specifics because of disclosure issues. But, understand that already a HUGE amount of work has been done behind the scenes and most other researchers don't yet know of what's to come.
.18um fabs could easily be refitted with strained Si material and compete with the .13um fabs. Actually, it's even better than that--the increases in mobility have been up to 8 times over that of Si.
CMOS isn't going to die. Turns out that we're not limited in the horizontal direction like everyone predicted years ago (remember how lithography was always the big problem?). Instead, it's the vertical direction. Our gates are having to get too thin. SiO2 just doesn't work well with 10A thick layers because of trapped charge and whatnot. Also we can't properly control doping at very shallow levels.
But all that doesn't matter. Strained-Si technology is where it's going. If you're interested, check out AmberWave. It turns out that we can increase the mobility of holes and electrons--so even older
No, CMOS isn't going to die. It's going to change and morph. Just like it has in the past. We don't need a revolution like many engineers are claiming--we simply need evolution. Strained Si is an evolution that will make for revolutions later. Current fabs can just swap out their current Si wafers and get strained Si ones--most everything else in the fab stays the same. Talk about a huge cost savings to boot (no need to rebuild a new fab for billions).
Long, cute, or funny Sigs are just another form of over compensation, used by geeks, nerdz, etc.
Here's a few quick explanations of some of the key points mentioned in the article.
The leakage problem: This is a really difficult and nasty problem. It arises from the fact that designing a chip involves trading off a number of things, among which are clock frequency, operating voltage and power dissipation. It turns out that as you increase voltage, it speeds things up but it also causes power dissipation to rise as well. Ask any overclocker. However, the speedup is roughly proportional to voltage, while the power dissipation goes as the square of voltage. Hence the operating voltage of chips has steadily been decreasing. The bleeding-edge research type chips are down somewhere in the 1V - 2V range. The problem here is that there is a fundamental property of the FET called the threshold voltage, the voltage at which (more or less) the transistor switches from being ON to OFF or vice versa. Of course it's not a sudden transition, so its desirable to have the system voltage higher (say by 2X to 5X) the threshold voltage, so that the transistors are turned ON and OFF fully. Otherwise, leakage occurs, and can become a very significant power drain if not kept in check. The problem is that due to physics and some other factors, the threshold voltage cannot be reduced easily past a certain point. There are tricks that the designer can use to attack this, but it's still a very fundamental issue. So what the circuit designers end up doing to meet the design criteria is play a large game of cost-benefit analysis with regards to power, frequency, system voltage, threshold voltage, area (die size), etc.
Masks: Integrated circuits are build up in layers. An extremely simple design might have 6 layers, modern CPUs might have 20 or more layers. Each layer is created with a mask that defines the features of the layer. While enlargement/reduction is used (meaning the mask features are larger than the features on the wafer), mask creation is still very difficult. It's like making a stencil with millions of tiny features. The photolithography involves very expensive machines with extremely precise optics. Indeed you might have heard of the push to "extreme ultraviolet" - this refers to the light source which shines through the mask and exposes features on the silicon wafer. The trend is to use smaller and smaller wavelengths, because the feature size keeps shrinking. The wavelength of light that is used must be significantly smaller than the smallest feature, otherwise you get interference/fringing/etc. Anyway, these masks are very expensive to produce, leading to very little room for error. You want to be sure that those masks are at least functional, and hopefully as bugfree as possible. To a certain extent you can work around some hardware bugs, but it's very stressful because of the huge cost and time delay (many months) of getting a design fabricated. Imagine what development would be like if compiling your source code one time cost you a million dollars and took 6 months. Now try to stay competitive in a market where everybody is screaming at you to get a product to market as quickly as is humanly possible. Simulation is the name of the game here.
Interconnects: This refers to connecting together the individual transistors to form blocks, connecting the blocks to form modules, etc, up higher and higher levels. Interconnects do not scale well, it's just one of those complexity things. The number of interconnects goes something like N^2 (where N is the number of transistors), and this can quickly get out of hand. The problem is you can't just make the wires longer (by wires I mean the etched paths inside the chip, not the external things) because this increases their resistance and capacitance, which means that they must be driven "harder" to achieve a given performance. To drive them harder you must spend extra area on larger transistors (which just complicates things -- now the chip is even more spread out) or spend more power, which is usually not feasible. A stopgap measure is to use copper instead of the traditional aluminum for the interconnects, but this is only really a one-shot thing, it only buys you so much. Another way is to use more interconnect layers (expand in the "z" direction) but this has its problems as well. The most promising solution to the interconnect issue is with advanced CAD algorithms and plain old good design. Keep related modules close to each other, and design busses to shuttle things around longer distances.
Capacitance: Capacitance is one of the worst enemies of the circuit designer. It means that on every transition of state, energy must be spent charging (or discharging) a dielectric. This is one of the main reasons for reducing smaller feature size -- smaller things have less capacitance. The article mentions fully depleted SOI, which is basically a very extreme way of trying to reduce capacitance. The bulk substrate is silicon dioxide, an insulator, instead of pure crystalline silicone (a conductor.) The effect is to decouple the individual transistors from the bulk substrate of the wafer. The result is much less stray capacitance, but the cost is that your transistors no longer work quite right so it makes circuit design that much more complicated. The article also mentions high-k dielectrics, which basically is a way of increasing the "gain" or drive strength of a transistor without increasing its size, which is the normal way of doing things. It can be really quite frustrating: if a path in your circuit is too slow, you have to increase its drive strength. But this also increases the capacitance (which leads to more power dissipation) and now the thing that drives that circuit also has to be bigger (to compensate for the increased gate area), etc, etc. Any means of increasing the drive strength without increasing area is quite beneficial.
I hope that was of some use to at least someone.