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Intel Itanium 2 Benchmarks
Pablo writes "Over at VR-Zone we saw some
interesting benchmarks of the upcoming Intel Itanium 2 processor codenamed
McKinley that is on schedule to be launched during second half of this year.
With a faster 3MB on-die L3 cache, 6 instructions/cycle and 6.4GB/s of
bandwidth, it is poised to perform at 1.5-2x of the current Itanium processor.
There is an overview of how the Intel Itanium 2 at 1Ghz clock frequency will
perform against the current Itanium 800Mhz and Sun's Ultra Sparc III RISC
processor."
Not to mention 130 watts of power consumption. And you thought Athlons were hard to cool!
well I'm sorry but all the benchmarks seem to be cache hitters and so run pretty damn fast
real systems are about BANDWIDTH
memory bandwidth/latency is the reason AMD killed the P4 in benchmarks
lets see INTEL go up aganst a SUN on a large oracle DB then I will take notice
really this is where SUN make their money
regards
john jones
I have had the chance to work with a McKinley box for a few months now, and it is with no doubt the fastest chip in the West, especially for some applications like public key crypto algorithms.
Indeed, McKinley running at 1 GHz can do a 1024-bit private key operation in 0.2 milliseconds - something well beyond any other existing processor. For high-volume secure electronic transactions, McKinley rules.
Site is slightly slashdotted, and most of the data is in gifs. Here's a fact or 2:
Intel's claimed specint2000 and specfp2000 are both about 1.75x the 800MHz itanium. And this with only a 25% clock speedup to 1GHz.
They claim specint2000 is 1.3x Sun Ultrasparc3 1050MHz, and specfp is 2x.
Unfortunately, there is no indication of what the frequency headroom/scalability might be. The main point of the pentium4 architecture is to scale to 4+GHz. Can we assume anything similar for the itanium?
Actually, current compiler technology can probably optimize quite well for a VLIW architecture. The only catch is that for it to work properly, you will need to profile your code. But with that data, a good compiler that can figure out where to optimize shouldn't be that hard to write.
What I really don't get, though, is why no one is focusing on using JITs with these. It strikes me that this is the ideal platform for a JIT, where it can recode parts of the program on-the-fly based on where the bottlenecks are and so forth. I mean, wasn't this the whole point of a just-in-time compiler in the first place? IBM's Java runtime can rival C++ in speed if it is allowed to run for a reasonable length of time, allowing the code to become truly optimized, and since Intel is targeting this thing in a server environment where applications will run for a similarly long length of time I fail to see why they aren't going that route. This has the additional benefit that as our understanding of how to optimize for VLIW improves, the programs do not need to be recompiled, but instead can immediately get the benefit. (I am fully aware that Itanium is supposed to do some of this type of optimization itself, but current specs are utter crap, to put it lightly.)
Interestingly, Sun's MAJC architecture does exactly that, expecting that a JVM or similar virtual machine will run on top. I have no clue what happened to that chip, but it struck me that it had much better potential to kick ass than Intel's Itanium despite having similar designs precisely because it was designed for a JIT to be on top.
The reason they compare to different Sparc is because not all benchmarks are available for the newest one (Sun is playing the game too and is only publishing benchmarks where it serves marketing).
Note that Sun has been cheating on Spec, that's the only way they can make recent Sparcs look competitive. It's a shame that it will force every other vendor to cheat in the same way.
SledgeHammer won't compete with McKinley, but with McKinley's successor, Madison.
Oh, good luck to AMD...
"MIPS is dead on the workstation/server scene, SGI went the Itanium way...MIPS is today almost only for embedded devices."
I'd love to know where people hear these kinds of things! I'd like to find the source and plug it good.
MIPS is SGI's primary platform for their worstation and server product lines. They will shortly be releasing Itanium based servers running Linux but they have stated again and again that MIPS/IRIX and ITANTIUM/LINUX are seperate product lines. Some of SGI's troubles stem from the fact that Intel is 2+ years late brining Itanium to market, they bet the farm on somone elses vaporware instead of their own (H1 & H2).