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Clockless Computing

Posted by michael on from the beat-of-a-different-drummer dept.

ender81b writes "Scientific American is carrying a nice article on asynchronous chips. In general, the article advocates that eventually all computer systems will have to move to an asynchronous design. The article focuses on Sun's efforts but gives a nice overview of the general concept of asynchronous chip design." We had another story about this last year.

3 of 342 comments (clear)

  1. Intel, AMD, etc and marketing by Alien54 · · Score: 5, Insightful
    So ...

    if we have clockless computers for the desktop, HOW will Intel and AMD market them?

    After all, a large quick and dirty rating they have used for decades is the clock speed. Throw that away and what do you have?

    I can see the panic in their faces now...

    --
    "It is a greater offense to steal men's labor, than their clothes"
  2. Re:"Bucket brigade" analogy unconvincing... by Rupert · · Score: 4, Insightful

    It's more accurate if you think of the amount of water getting to the other end. If the water supply is irregular, the synchronous bucket chain will sometimes be sending empty buckets. The asynchronous bucket chain only has to send full buckets. If one person is 1% slower than the others, the other people on the synchronous bucket chain have to wait a whole extra cycle, reducing throughput by 50%. Throughput on the asynchronous bucket chain is reduced by just 1%.

    --

    --
    E_NOSIG
  3. Re:Heard about this stuff in class by William+Tanksley · · Score: 5, Insightful

    It's amusing to read the claim that an asychronous chip couldn't take advantage of pipelining. You see, the thing is that pipelining exists ONLY to control two of the disadvantages of clocked processors.

    First, it allows different instructions to complete in different amounts of time. An asynchronous chip wouldn't have that disadvantage.

    Second, it allows 'idle' portions of the chip to be used by other instructions whose time hasn't come. Asynchronous chips are vulnerable to that as well, but they can be much less vulnerable than even the most pipelined architecture, because dataflow can completely guide the chip: you can hammer in more data as soon as the previous data's been slurped in.

    So far from not taking advantage of pipelining, asynchonous chips naturally have one of the advantages of pipelining, and can be built to have the only other.

    -Billy