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AMD's 64-Bit Chip
EyesWideOpen writes "AMD is set to release a 64-bit chip early next year which will be completely backwards compatible with the Athlon line. The current 64-bit offering from Intel, Itanium, is an entirely new chip that has no backwards compatibility with its x86 line of chips (from the 8080 chip to the Pentium IV) and is designed only for high end servers. AMD's solution to this problem is the Opteron chip (product info) which will be in servers, desktops and laptops. Here is a wired article."
What's the point of making something that is unsupported by a large chunk of today's software
Because you end up with a CPU that has layers of compatibility upon layers of compatiblity.
you'll have real mode, protected mode and now probably something like 64 bit mode.
imho it's better to get rid off all the old junk and start over once in a while.
> imho it's better to get rid off all the old junk and start over once in a while.
Unless of course you've got an installed base somewhere in the billions, 20 years worth of compiler optimization, a factor of, what 100, more people that know the assembly language, etc. And it doesn't help if good compilers won't exist by the time your chip comes out. And if the internal interface teams have difficulty communicating, you're going to be late, hot, slow, and over-complicated.
Starting over is nice from a design perspective, especially because it feeds the urge for creativity that most engineers have. Unfortunately, that do-over is not always executed well, and it turns out to be a little underwhelming, just like Itanium.
Fight the urge to think that all new things are good. Please.
Outside of a dog, a book is a man's best friend. Inside a dog, its too dark to read.
A properly designed 64-bit CPU does not need to 'run slower' to run 32-bit apps. AMD came up with a simple solution to the 32-bit limitations of X86 code: they added a new 'mode' to the processor to run 64-bit binaries. when this mode bit is set (similar to the old Real and and Protected modes of X86 chips), the chip utilizies the full 64-bit-wide pathways for data and cacluations, when this bit is not set, only the lower (or is it upper? AMD isn't saying...) 32-bits of the pathways are used. The same exact logic units are used for all 32-bit and 64-bit calculations, only the bit-depth precision changes. Thus if it takes an ADD instruction 16 cycles to add two registers and store the results in a third register, it takes 16 cycles reguardless fo whcih mode the processor is in. Of course, AMD also added an extra 8 registers for use in 64-bit mode... very useful.
The itantium does not get the majority of it's speed from being 64-bit - this is a common mistake people make. It has a _very_ different design and instruction set - EPIC - which places the burden of parallel instruction determiniation on the compiler. Basicly, they used the oldest software refactoring trick in the book, but on the whole processor design: they examined the amount of time spent executing, and looked for the bigest runtime performance-hit that could be moved from a O(n) to a O(1) penalty by simply moving the calculation. In this case, modern processors spend a great deal of time trying to handle multiple instructions at once, which may or may not be parralellizable (is that a word?) - thus the processor has to figure out, on the fly (in a P4, for example), if it can execute the next four add instructions in parallel, or if they are interdependant and cannot... By placing the burden of parellelism determination and instruction scheduling on the compiler, intel made the compiler writer's job much harder, but at the benefit of increased performance.
Oh, and most PDA processors are much more traditional, and thus don't require complex compilers like the itanium, so actually porting a compiler (or an assembly-lang app) to a PDA from x86(32-bit) is easier than creating one for the EPIC architecture.
And yes, I know the above is an oversimplification, and Intel and AMD both did a lot more, in a lot more detail, on thier 64-bit chips.
Oh, and I think the next few iterations of itaniums _will_ beat the AMD 64-bit chip on bechmarks. But not by a landslide.... And with the differences in price (EPIC chips are Expensive... capital E) the AMD chips will win the hearts of many and be the performance-price ratio king. And who wants to pay 3 times as much for 20% more performance?
man is machine
If you want a "fresh" architecture that isn't full of old junk, buy an Alpha. Or for that matter a MIPS, SPARC, or Power4. All of which are 64-bit and have either always been 64-bit, or at least had their original 32-bit designs planned around 64-bit expansions.
Personally, I think it's amazing how much old crap has been piled onto x86. It's really remarkable it runs at all, and it's even fast! I used to turn up my nose to the x86 given how they piled all the 32-bit extensions on the old 16-bit core. It's really a travesty. And the actual instruction set and register set looks like a damn train wreck compared to MIPS or PPC. But they are soooo cheap I eventually got over it, and just try to avoid thinking about any level lower than 'C' now so I don't go insane.
The vast majority of the old cruft in the X86 architecture that nobody uses any more has been demoted into microcode or other non-optimized crevices. Ever since the Pentium came out, good programmers and compilers have been using an almost RISC-like subset of the X86's myriad possible instructions, operands and addressing modes. IOW, all that old stuff really doesn't slow things down in the real world.
Anyway, recent CPUs have been transforming X86 instructions on-the-fly into bizarre internal parallelized architectures anyway. This hidden logic is an order of magnitude more complex than what is visible in the X86 instruction spec. The implementers are free to completely redo the hidden stuff with every new generation of X86 chip.