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New Power Macs Have Crippled DDR Memory?

eggboard writes "According to Rob Art Morgan, who has tested this, the new Power Macs from Apple that use DDR (double data rate) memory -- like the Xserve rank-mount unit -- cannot access the memory any faster than the cheaper and slower SDRAM found in the previous system arch. A controller limits the data rate to 1 GB/s, while DDR could work more than twice as fast. Unfortunately, this makes mincemeat of the architecture, as it bus-/memory-bounds 2D and 3D graphics and rendering."

6 of 82 comments (clear)

  1. Re:Meet the new boss... by foobar104 · · Score: 5, Insightful

    You haven't the slightest idea what you're talking about, do you?

    Motorola makes the CPU. Motorola makes CPUs that don't support DDR access to memory.

    Apple makes the motherboards. Apple implements DDR memory everywhere except in the CPU.

    IBM just announced vector computing support in the Power4. Vector computing is a big part of Apple's strategy, and until recently it was only available from Motorola.

    The new Power Macs have a heat dissipation mechanism that's capable of dealing with many times the heat load of the currently shipping systems. They added this feature despite the fact that the previous generation of Power Macs had no particular heat problems.

    Can't you read the writing on the wall? Apple has designed this new Power Mac to accept new, faster processors, and lots of 'em. A four-processor system is not unreasonable given the amount of space and heat dissipation inside this new chassis. Six or eight processors might even be possible, if everything comes together just right.

    Don't assume you have the first idea what Apple has planned until you get all the facts.

  2. Server? by SteveX · · Score: 5, Funny

    My rackmount server is going to suck at 3D games. Crap.

  3. Misinformation at it's finest by h0tblack · · Score: 5, Informative

    So we have an article which misses a few important points at the generally iffy barefeats, this is then compounded by the comment "cannot access the memory any faster than the cheaper and slower SDRAM" which misses the mark even further. It's a real shame when these things spread around as "the truth" especially on somewhere like slashdot.
    Yes the new motherboards are not full DDR, this is mainly because the processors available from Motorola cannot handle DDR FSB's and therefore a full DDR motherboard. This is a shame, but it is far from crippled DDR RAM. Many early DDR RAM x86 motherboards were the same, only the RAM was DDR, not the full motherboard and processor FSB. While this does mean there is still a bottleneck (in certain tasks) between the processor and other components there are advantages to having DDR RAM. The tests at barefeats are using purely CPU limited operations, which will obviously show no real improvement as there has been no CPU or bus change (although the new 1Ghz procs have only 1Mb of DDR L3 cache versus the old 2Mb DDR and a 167Mhz bus version is available). What DDR RAM will help with is when there are a variety of components (CPU, HD, network, AGP, PCI, Firewire, etc) all vying for valuable memory bandwidth. It's these 'real-world' situations when we will see a performance increase. If you just run single process, purely CPU intensive tasks then maybe these machines aren't for you, but if you run a lot of stuff at the same time, or anything that uses CPU, HD, AGP etc intensively and concurrently then you should see an improvement. Things like Quartz Extreme will be throwing a LOT of data at the AGP bus, with DDR RAM this won't have to wait it's turn while say your CPU is busy grabbing all the bandwidth. I'd say many users have a lot of HD, CPU, GPU and network activity going on simultaneously, especially 'power' users. Hopefully we'll see some more benchmarks that show a variety of tasks being performed on these new machines once more people (and more reputable sites) get hold of the machines. While not fulfilling everyones dreams, I'm sure that the statements about the DDR RAM additions being a "waste" or "crippled" will be shown to be entirely false.

    1. Re:Misinformation at it's finest by stux · · Score: 5, Informative

      Running fully optimized AltiVec code all G4s are currently memory bound for most operations

      It is really really hard to keep a dual 1Ghz machine fed when a single instruction (taking a single cycle) can process 16bytes of information.

      If you had a simple filter for example, a blur.. that could be executed in perhaps 10 cycles...

      which would require 3.2GB/s of bandwidth to run at full speed (1.6GB in, 1.6GB out), and on a dual... 6.4GB/s (which happens to be the bandwidth on that new IBM PowerPC ;))

      The current bus can only provide 1.3GB/s

      Which means this filter would run at 40% of the full speed...

      If its running on two cpus, then its going to run at 20% of full speed.

      This means DDRing the bus would double the performance... but you'd still only be running at 40% of full speed.

      AltiVec generally converts almost any relatively complex operation into a memory benchmark.

      Since altivec is used for the most time critical parts of a program, faster memory would allow these time critical parts to run x times faster...
      Anywho, when it takes only two cycles to multiply 16 values by another 16 values, then add another 16 values, and saturate the result (something which would maybe take 80 cycles without altivec, memory bandwidth becomes the limiting factor. (for those counting that's a 40x improvement, the equivalent of a 40GHz chip if it was running scalar code)

      Its even worse on 7450s because the AV unit can execute multiple instructions concurrently.

      G4s *ARE* memory constrained, I'd say even seriously.

      Small benchmarks will not expose this as they'll almost always run out of L3, or even L2 (L1!) cache.

      BUT real world operations normally work on massive data sets...

      (be it video, audio, 2D, 3D, genetic sequences, or just your window being composited with a menu)

      Incidentally, the speed improvements from altivec can generally be worked out as 4x, 8x, or 16x for most uses depending if you can use 8, 16 or 32bit math. Some operations can make use of tricks altivec can do and scalar can't. which allows speeds of 32x (or even more)

      Running a highly optimized calculation which is NOT memory bound we've managed to come up with some interesting numbers ;)

      The algorithm was highly optimized for MMX and AltiVec,

      running on a single G4/500, with many other applications running etc, the calculation was over twice as fast, as the same calculation on an athlon 1.3Ghz. The G4 has a 100Mhz bus, the athlon has DDR266, but it doesn't matter because the process is not memory bound.

      this means it took 15 mins on the G4/500 and 30mins on the athlon/1300.

      (the athlon was running NOTHING else)

      --

      ---
      Live Long & Prosper \\//_
      CYA STUX =`B^) 'da Captain,
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  4. Re:Can someone please explain by LenE · · Score: 5, Informative

    IBM won't license Altivec from Motorola, so they can't make the "G4" Chips that Apple wants and needs. Actually, if I remember right, it was an Apple Engineer who came up with Altivec, and Motorola implemented it because they could also benefit from it.

    Unfortunately the AIM alliance partners seem to have increasingly divergent needs from the partnership. IBM wanted PowerPC for servers, and sees Altivec as a gaudy tack-on to their architecture. They still produce the "G3" chips, at ever higher and higher clock speeds. Apple can't use them though because of the MHz. myth. IBM's stance towards Altivec appears to be weakening though with their upcoming chip.

    Motorola wants PowerPC for embedded stuff, and Altivec makes it easy to do DSP like functions in a general purpose processor.

    Apple needs the PowerPC for everything but the iPod. They need Altivec to make MacOS X so cool for consumers and scientists. Since IBM won't license it, they are stuck with the only producer, Motorola.

    It's times like these that I wish there were some truth to the old rumors about Apple buying Motorola's PowerPC fabs. If that were the case, Apple could produce the exact chips that Apple needs, not what IBM or Moto wants. Unfortunately, there isn't any indication that this would be profitable or feasible for them.

    -- Len

  5. Wrong, wrong, wrong by Aapje · · Score: 5, Informative

    Altivec was created in a joint effort between Apple, IBM and Motorola. They all have patents on the thing, but use different names for it. Motorola owns the name Altivec, Apple the name Velocity Engine and IBM used to call it VMX. AFAIK they all have the right to use the instruction set (but not a name or specific implementation they don't own). The reason why IBM didn't use it was because they didn't see the use of a vector processing unit (in the past). Of course, the G4, Pentium III & IV and the Athlon have shown the usefulness of a vector unit and IBM has changed their stance. The best proof is of course the new 64 bit PowerPC. It has a vector processing unit which almost certainly is Altivec (although they won't use that name). The Power5 will probably contain a vector processing unit as well.

    It is clear that Motorola and Apple have grown apart. Apple has had big problems with them for a long time and has looked at other options. They didn't choose to buy Motorola's awful fabs, it's too late to do that know (nor is it smart). No, credible rumors point to IBM. It makes a lot of sense:
    - IBM wants to sell more low-range (Linux) servers, so they already need a fast desktop CPU. Why not sell it to someone else as well?
    - Apple has a lot of experience with Altivec, it makes sense to work with them to produce this chip (Apple employs some very smart chip-designers).
    - Altivec is a respected instruction set. It's proven to work (no need to reinvent the wheel on a risky venture). Tools are available. GCC supports it (and since their servers will run Linux...).

    In 6-9 months we'll probably have a 64 bit PowerMac that is very competitive. I can't wait.

    --

    The Drowned and the Saved - Primo Levi