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AMD Opteron "Hammer" Preview
Melvin Tong writes "Hardware Extreme has posted a preview of AMD's 8th-generation processor that AMD is currently developing with a few exclusive pics of the mechanical sample. AMD Athlon processors based on Hammer technology are expected to ship in the forth quater of 2002. The preview is located over at HW Extreme."
Clearly a blatant rip-off.
General Relativity: Space-time tells matter where to go; Matter tells space-time what shape to be.
I won't bother to elaborate on what several others have already mentioned, that this is a poorly edited stored pasted together from AMD press releases. The total kicker on this is the very last 'next' link takes you to a pages to buy some AMD Athlon chips!
The boundry between news and advertisement gets more porous each year...
Peace, or Not?
The NDA isn't quite up until 2400 USA (eastern? pacific?, don't ask me i don't know) time, but look at, Here
Expect reviews from the usual suspects.
AMD have modified there ratings a little so as
to keep the model numbers fair compared with
the newer faster Northwood pentium 4s. So while
the old rating system would have had 2400+ as a 1933MHz Athlon, and 2600+ as a 2066Mhz Athlon, in
fact the 2400+ is the first 2GHz Athlon while the
2600+ clocks in a 2133MHz.
We can expected newer Athlons to be released later
with 333MHz Front Side buses, and later 512MB of cache. Even when Hammer comes out, AMD will still to selling Athlons for around a year afterwoods, the Athlon will move done the low end to replace the Duron, and thats going give the celeron a real kicking. In fact Intel seems to have blown
there wad completely, with nothing to compete with
the Hammer until there Prescott strink of the
P4 in Q4 2003.
That may be, but if you want to take a look at some of the serious articles on ememory & clock latency (from the CPU's perspective) you'd realize why they are adding the memory controller where they are. A 'normal' SDRAM memory controller on a VIA or AMD motherboard for instance can easily take 70+ cpu cycles before returnign the required data... So unless the cpu has other data to process (which fits into the cache) then it just sits there til it has the data requested... With a cpu built-in memory controlelr of this sort (especially if they allow tolerences for faster rated memory within the existing class) could lower the latency down to say 6 cycles...
This is great for memory intensive & system intensive tasks (from gaming to high demand servers)...
we are all invisible unless we choose otherwise
CPU designs are pretty modular. It shouldn't be hard at all to swap in a new controller when the time comes. If the internal hardware interfaces weren't very clean, design would take a lot longer.
Copyright Violation:"theft, piracy"::Anti-Trust Violation:"thermonuclear price terrorism"<-Overly dramatic language.