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AMD's Athlon XP 2700+
kraven_73 writes "According to some Taiwanese sources, AMD will officially reveal its Athlon XP 2700+ processor on the 7th of October. Most interesting is that this CPU will have a 333 MHz FSB. The first implementation of this increased FSB on Athlon platform. It is expected that the novelty will be based on the latest Thoroughbred core stepping 1, just like the current Athlon XP 2400+ and 2600+, and will work at 2.17GHz."
I'm not normal, but here's a few from my background
Video editing. Nothing out there is remotely fast enough for what I want to do, and what I want to do is pretty limited.
Computatational chemistry. Nothing out there (or scheduled for the next ~100 years) is fast enough to do the simulations people are really interested in.
License key cracking for those companies who decide to use encryption. :^)
"Seven Deadly Sins? I thought it was a to-do list!"
Depends what you define as a northbridge, and what you define as a FSB. The bus type (EV6, HyperTransport, whatever) is just a name for the signaling and protocol - the name of the bus itself can still be "Front Side Bus".
The "traditional" northbridge had a memory controller and an AGP controller, as well as a PCI controller. The PCI controller got moved completely off the North Bridge to the South Bridge and replaced with a proprietary interconnect in a lot of modern chips. The memory controller was moved on die, but the AGP controller is still off-die, and thus needs a chip for it. This chip could be called the "north bridge". It's just a name - AMD calls it the "HyperTransport AGP 3.0 Graphics Tunnel" (which doesn't really make much sense, as it also has a HyperTransport link to a south bridge - how does THAT relate to graphics?) but it's still a North Bridge, just without the memory controller.
There are two HT links on the system, which is why it makes sense to call it a "north bridge" and a "south bridge": there's a HT link from the CPU to the North Bridge (the AMD 8151) and a HT link from the North Bridge to the South Bridge (the AMD 8111).
So, yes, they do have a FSB, unless you want to call it something else: "highspeed HT link" and "lowspeed HT link" (for the North Bridge-South Bridge interconnect) maybe? Got me. It doesn't matter. The FSB has always been the high speed link out of the processor to a bridge chip, which then has a low speed link to another bridge chip which has all the PCI, LPC, ethernet, all that crap. Hammer doesn't change that, it just removes the memory controller from the North Bridge.