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Understanding Bandwidth and Latency
M. Woodrow, Jr. writes "Ars has a very eye-opening article on the real causes of bandwidth latency and why we should just drool endlessly over maximum throughput issues. In particular, I think the author's look into the PowerPC 970 and the P4's frontside bus is interesting considering how we're constantly being told by marketers that more speed is always going to translate into massive performance gains. The issue is, of course, far more complex, and this article does a good job of thinking about the problem from an almost platform agnostic point of view."
>1000 posts. [slashdot.org] I'll drink to that.
I'd buy that for a dollar!
(Where'd dollarman go, anyways?)
You (Jay Carlson) are wrong about your criticisms. A standard normal mac gets over 20,000 512 byte read IOs per second thorugh SCSI Manager 4.3 and a decent Fibre Channel card from a variety of vendors, including Astera Technologies, and even probably ATTO. Thats only 10 MEGABYTES per second.
10 MEGABYTES!
What idiot mac-bigot thinks you need PCI-X for merely 10 megabytes per second to function and doubts the figure? Why do you say "There are no Macs that support PCI-X. I am therefore suspicious of the numbers you claim for this configuration."??? Is it because you know NOTHING about PCI-X cards? PCI-X cards are backwards comaptible with PCI slots and work in 32 and 64 bit slots and at speeds from 33 to 133 Mhz inclusive. Thye would sell almost none if this was not the design goal.
I find it hilarious that you tried to find anything wrong with the post. In fact that speed is for ONE CHANNEL on a card. Most of the expensive 2,000 dollar cards have TWO channels on them. I think you really know very little about computers or at least about high end laser IO technologies..
Lets look at your other criticisms of the post. You stated "And where are these benchmarks?" The random read and write benchmarks are very common, and you can write your own its quite easy. You merely write a loop with IO data dependencies at various points and touch no more than 4 bytes from each cacheline and try to avoid hitting the same 4K page area for a while during the test. (hop through memory rapidly adding values) All the standard portable memory test programs that measure mobo latency for SIMULTANEOUS read and writes show the non-DDR macs as faster than AMD. Why do you feel the need to complain about it? Wasn't there a HUGE article at the top of this thread that tried to teach you about latency issues when biasing a system for stream speed access?
True backside cache origianally meant "no hope of cache coherency" by the way. Its what is meant by that phrase. If you want to pretend that there is no difference between all categories of L2 on-chip cache, then why even define L1? Sometime they both run at same clock speed. YOu need a new term for non-MP L2 cache in your view. The world aready created a term.... its called BACKSIDE CACHE. Deal with it.
Thats why you have to have a PIII and not a P4.... its L2 cache is hidden and cannot be retrofitted with any technology aftermarket to "just need a cache coherency protocol between your processors". YOur words make me laugh.
At this point I hardly think you are qualified to criticize the post. I think you are an envious Mac-Bigot, but I will address the rest of your pathetic statements as well.
YOus said "there is no penalty for use on later CPUs." Bwaaa ha haaaaa!!!! You must be crazy! misaligned integer accesses are very bad on PowerPC. Worse yet... the article is talking about MACINTOSH, not unix OS on a mac such as Mac OS X. Google clicks show millions of accesses per day by macs and 90% run OS 9 and older "classic mac". Only 10% run FreeBSD-based OS X. OS X is NOT the MAC, and has nothing to do with the mac other than that nowadays it runs on some of its models, but so does OS9. Compilers such as mettrowerks and from symantec lacked the ability to type and use Pack(1) from the beginning of the mac to just last year. Just because GNU supports crap like that has nothing to do with the mac programming world. Why you tried to find another mistake and failed is hilarious. Go ahead, misalign a few integers in some benchmark code and watch the speed plummet. ITS SOMETIMES handled in software as an exception! And when its in hardware its still much slower.
You tell people to buy Alpha and Hammer to get more fast RAM and don't realize that the article explains that solutions like Itanium and XEON are rich man solutions, and that running shrink wrapped software is desirable too. How much shrinkwrapped software runs on Alpha boards?
Why do you even try to comment negatively.?
You type "Why wait? Apple isn't the only vendor out there." regarding 40 bit physical addressing. You cannot use a Pentium 4, or a AMD "non-hammer" for 40 bits, so your suggestion is to run an expensive server box that is unsuited for running most software. At least with Apple, one day machines will have >32 bit physical addresses and still run countless software packages. Apple in its version of UNIX is already 64 bit clean for all its IO all the way up through the kernel, as well as prepared on the PCI DMA side, and the user task scheduler side.
I can't believe your pathetic post got +3 with not one factual statement whereas the original post you tried to criticize had over 300 factual statements.
Obviously anti-mac bigotry runs strongly on slashdot today. Unless all your "fans" are yourself Jay Carlson.
I think you tried to run RC5 on non-PowerPC systems and got grumpy or envious at the mac performance and think that there is no reason to ever shift bits in a register!?!? Even the 32 bit shift (not 64) on a pentium 4 is horrible, but I suspect you are a fan of AMD instead... or a disgruntled stockholder.
As it stands you found NOT ONE mistake in the post you are trying to slam. Though you do point out that Alpha based computers might be available and might be affordable that accept more than 4 GB of RAM.... but I doubt they are as affordable as you think they are.