Bringing Back the PDP8

Anne Thwacks writes " Andrew Grillet has decided that the Digial PDP8 - the first ever minicomputer, will rise from the dead. He is calling it the PDQ8. Sure others have done software emulations, and even hardware clones, but he is not just building a hardware clone, but trying to revive the whole idea of 12 bit computers!"

Comments

Calling all Electrical/Computer Engineers

[ekrout]

Many of you probably have used Xilink's 1000, 2000, or 4000-series FPGA card during laboratories for your undergrad classes.

Well, if you'd like, you can follow this design of an FGPA implementation of the original PDP-8 computer!

If you've used Verilog (a hardware design programming language), like I have, you can even download all the code!

Just how big *were* these things?

[ekrout]

Well, I found this old link in my bookmark manager. It details the history of EMS (sound studio) in vivid detail, including a listing of all their original equipment.

The interesting part is that they posted high resolution images of their setup, which includes PDP-8 microcomputers!

The image: http://www.ems-synthi.demon.co.uk/studiopz.gif
The PDP-8s:
Left side - Teletype for PDP8
Left bay - PDP8/L Computer ("Leo") 4K x 12 bits (=6K bytes) 1.3 s cycle (0.77MHz), 32K Hard Disk Store
Center left bay - PDP8/S Computer

Re:what for

[Detritus]

Probably OS/8, which if I remember correctly, was a multi-user operating system. You can run a multi-user system on a PDP-8 with 32KW of core.

Re:what for

[dhogaza]

OS/8 was a single user system. I wrote a multi-user kernel that ran multiple copies of OS/8 customized to hook into device drivers supported by my kernel. It supported virtual paging using a hardware hack first suggested by Richard Lary (the author of OS/8). We ran four or five users on a 32KW 8/E with a couple of RK05 drives.

We never distributed it because paging performance without the hardware hack was very bad (every CDF instruction needed to be trapped and mapped in software) and the hardware hack was only developed for the 8/E and piggy-backed on one of the system boards destructively (i.e. once modified your 8/E wouldn't run without our hardware).

But it was used internally by the company I developed it for until about ten years ago.

Re:Didn't these things have selectable word sizes?

[HotNeedleOfInquiry]

"or am I just remembering some strange dream? "

It's a strange dream. The only 8's that had a knob on the front were PDP 8/e, 8/f, and 8/m and they all shared basically the same front panel design. The knob selected the register that would display on the front panel. It had no effect at all on the operational mode of the machine.

Re:12 bits

[sql*kitten]

Maybe someone would enlighten the rest of us on why a certain bit size is better than another, and why we currently use 8/16/32/64, instead of 12/24/48/96 ?

This article explains why base-3 systems are actually a lot better than base-2 from a theoretical perspective, but that it was much easier to design hardware in base-2, so base-2 became the de-facto standard. Nowadays we could probably fab base-3 hardware fairly easily, but it's not worth doing so with all the base-2 hardware already in existance.

As for 16/32/64 instead of 12/24/48, it's just one of those things. IBM's earlier AS/400s ran on 48-bit processors (now they are 64-bit). 96-bit floating point is an IEEE standard. And do you know why file permissions in Unix are rwxrwxrwx? It's because they borrowed that idea from another operating system designed for 9-bit bytes and a 36-bit processor.

KW == "kilowords"

[red_dragon]

Back then, the size of core memory was generally measured in machine words, thus in the case of a 12-bit machine like the PDP/8 with 32 k-words, the core would be: 32 x 12 bits == 384 k-bits, or 48 k-bytes.

Why we use base 2 instead of base 3

[Anonymous Coward]

As nice as a base-3 system my be in theory, there are very good reasons for sticking to a base-2 system in hardware. As we are moving to smaller and smaller fabrication processes, it is necessary to lower the supply voltage Vdd. For example, now that we are approaching the 0.1um and 900nm levels (at least in research labs), Vdd is getting down around 1 Volt. However, the Vt (the threshold voltage needed to turn "on" a MOS transistor) stays the same, because it is determined by physical properties of silicon (mostly). That means we're losing headroom. To implement ternary logic, we would need 3 different voltage levels. We're simply running out of room to do things like that. You need to leave a noise margin around your "1" and "0" values for reliable operation. (For example, if Vdd=1V, you might consider 0.0-0.4 = "0", 0.6-1.0 = "1". Then a logic gate that "sees" 0.0-0.5 interprets it as "0", etc. If you had a "0" that was really 0.4V, you would hope that "noise" wouldn't bump it up above 0.5V, or else it would look like a "1".)

The threshold voltage for transistors is somewhere under 0.2-0.3V usually (depening on the technology & lots of other parameters). So, you absolutely need a 0.6V supply. (0-0.3 = "0", 0.3-0.6 = "1".) Unfortunately, even with Vdd=1V, you'll get voltage drops happening throughout the chip ("IR drops" - as in I=current times R=resistance) so that the 1V may only look like 0.8V to some parts of your circuit.

From the above discussion, it should be obvious that there really isn't room to shoehorn in a third voltage level. Also, a nice feature of CMOS design is that when a gate is sitting in a "0" or a "1" state, it is drawing no (well, negligible) power. Power is only dissipated while a value is switching from a 0/1 or vice versa. Off hand, I can't think of a way to do that with a third logic-value. Consider drawing even a tiny amount of current while a gate is sitting at logic "2" (or whatever you want to call the 3rd value). 1mA (milliAmp) times 1 million transistors on a chip = 1000 Amps. That chip's going to get a little hot!

Ok, so you've probably got at least two questions, which I will try to answer in advance. If you've got other questions - I'll just let someone else tackle those.
Q1) Why don't we just use a higher Vdd (supply voltage)?
A1) If you're using smaller transistor widths, you simply can't. When you use a really thin gate (i.e. 0.1um) on a transistor, the breakdown voltage of the gate is reduced. If you use a higher voltage, the transistor melts. (You could use larger transistors, but that kind of defeats the whole purpose! We make transistors smaller because we can fit more on a chip, and they operate faster and use less power.)

Q2) Can't we lower the threshold voltage?
A2) Yes, to some extent. (It's not always easy.) But we don't want to. Even when a transistor is "off", there is still a very small amount of leakage current flowing through it. If you reduce the Vth, you also increase the amount of leakage current. In older technologies, this hasn't been much of a problem, because the leakage current was so small in comparison to the dynamic power consumption. But as we are putting more and more transistors on a chip, the leakage power consumption in modern chips can easily add up to 30%-40% of the total power consumption. There's also another reason. If you did that, you would be lowering your noise margin. And you don't really have much control over the noise (which is why it's called that). If you reduce noise margins too much, you'll find it almost impossible to create a circuit that actually functions reliably.

Well, I hope that satisfies some of you (and doesn't get the rest of you too upset). VLSI circuit fabrication is a really neat field. Some of the tricks that are being used these days to fabricate that chip sitting in your computer and get it running at 2GHz (or aren't they up to 3GHz now?) are quite amazing - they're doing their best to cheat physics! Using a ternary counting system to build computers may have a lot of nice theoretical properties, but I can't see it displacing binary any time soon, except possibly in some really specialized applications. (There are always exceptions.)

That's my $0.03 worth. (Hey, I typed a lot. I think that's worth at least $0.01 extra. Maybe $0.025?.) Any errors in the above are mine, but I won't admit it.

Re:Why we use base 2 instead of base 3

[pjrc]

Off hand, I can't think of a way to do that with a third logic-value. Consider drawing even a tiny amount of current while a gate is sitting at logic "2" (or whatever you want to call the 3rd value).

It could be accomplished (fully static CMOS, no steady state current to maintain a 3rd logic level) with a second power supply, and circuitry designed to connect the output to either Vss, Vdd or Vmm (m for middle, for lack of any other name.. hmm) Brian Hayes's flawed assumption is that circuit complexity increases linearily with the number of logic levels. He writes "An obvious strategy is to minimize the product of these two quantities", refering to the radix and number of symbols to represent a number... but he just pulled that out of a hat. The required circuit complexity is not linear function of the radix, and a realistic model would quickly prove that binary is the most efficient. A fully static ternary output requires a minimum of four transistors, whereas binary requires only two.

That chip's going to get a little hot!

With a static CMOS circuit designed this way, power consumption would be approx 0.5 * C * f * V^2 (as it is in normal binary circuit). C will probably increase somewhat, as nearly twice as many transitors would be needed per circuit, yet fewer trits are needed that bits for the representing the same numerical range, so the increase in C probably wouldn't be by a factor of two. Presumably f (the clock frequency) would stay the same (well... I'll get to that...), and V stays the same (50% of transitions in binary are full supply voltage, in ternary 33% are full voltage and 33% are half voltage). Power comsumption would probably be similar.

Saddly, f probably won't stay the same. C gets larger on each signal, and when driving to half voltages, the transistors that would connect to the Vmm supply get only half the effective gate voltage applied. So doubling the load and cutting the drive significantly is really going to hurt the circuit's speed.

Dynamic logic tricks (pre-charged busses) and bicmos circuits add another interesting dimension that's too complex to worry about, though it'd be important for any microprocessor.

But power consumption isn't likely to be a problem.

Getting back to the old PDP-8, as I recall it was a binary machine. The motivation behind 12 bits was that 6 bits was ideal to represent both upper and lower case characters and plenty of symbols, and 12 bits (two chars) was plenty for useful math. I don't recall the popularity of 6/12 bit systems having anything to do with base-3 signaling.