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Understanding Pipelining and Superscalar Execution

Posted by chrisd on from the read-hennessy-and-patterson-first dept.

Zebulon Prime writes "Hannibal over at Ars has just posted a new article on processor technology. The article uses loads of analogies and diagrams to explain the basics behind pipelining and superscalar execution, and it's actually kind of funny (for a tech article). It's billed as a basic introduction to the concepts, but as a CS student and programmer I found it really helpful. I think this article is a sequel to a previous one that was linked here a while ago."

5 of 87 comments (clear)

  1. suck it by Anonymous Coward · · Score: -1, Troll

    no fp

  2. Optimizing by PhysicsGenius · · Score: -1, Troll
    This stuff is great to know if you are

    • Designing a chip
    • Designing a compiler
    • Very bored

    Otherwise, it is useless. Worse, "regular" programmers (meaning anyone not writing a compiler or assembler) will probably spend countless hours poring over this document trying to "squeeze out that last little bit of performance" despite the fact that Knuth proved performance is a useless metric..

  3. Re:Bad Timing by GigsVT · · Score: -1, Troll

    If these two articles, along with the promised third one came along a few months ago, I could have skipped even more architecture classes and still passed.

    Ahh, you're trying to go to college to actually learn stuff, rather than to stroke the ego of professors and get contacts for job leads into cushy jobs where skills don't matter.

    Big mistake. I tried to do that, but got too frustrated by the professors that based your grade on attendance rather than what you actually learned. Might as well drop out now. You will learn a lot more on your own anyway.

    --
    I've had enough abrasive sigs. Kittens are cute and fuzzy.
  4. IN SOVIET RUSSIA... by Anonymous Coward · · Score: -1, Troll

    ...party finds YOU!

  5. how to build a Bomb CPU! by Anonymous Coward · · Score: -1, Troll

    Hi americans, from Spain

    DLX+Pipeline+Superscalar+Tomasulo+VLIW+Hyperthre ad ing+
    multiple caches(L1+L2+L3)+multiple buses of RAM(dual,trial,..)+multiple modules RAM+
    (many ideas of people at Internet)+
    (please: better A = A op B than C = A op B to reduce the size of operation of instruccion to pack well at VLIW)

    =>

    design of CPU and GCC :) better than stupid P4 with MMX, SSE, SSE2, .. with owner compiler.

    JCPM (copyright)