Bright Peaks for Smaller Chips

Salden writes "University of Wisconsin scientists propose a way to create 20nm chip features. They were investigating the limits of X-ray lithography and discovered that they could control the phase of X-rays by adjusting the gap between a mask and wafer. Pretty cool."

Comments

Its not just the drawn length that matters

[twfry]

Already with 90nm processes, the height of the trans' gate is ~1.2nm. That's about 5-10 silicon atoms. The net result is you have to continuously lower the operating voltage to reduce current leakage. 90nm processes operate at ~1.0-1.5V.

A drawn 20nm process will have an even shorter gate height. What would we be down to then? ~1-4 silicon atoms? This would force the operating voltatge to be lowered even more, possibly approaching Vt. (I forget exactly but around ~0.7V)

I'm not saying that we'll never have a 20nm process, we will. But there is going to be quite a bit more involved than figuring out how to mask the waffer. i.e. double gates, etc.

Re:Its not just the drawn length that matters

[Bender_]

First of all, the parameter you are speaking of is not the "Gate height", but the gate oxide thickness. Dry oxidation allows very thin gate oxides, also below the current mark. Manufacturing these oxides is a comparably easy problem, however decreasing oxide thickness will increase the amount of current tunneling through the gate. This is going to be quite a problem in 65nm and below.

To circumvent these problems there are a multitude of options under investigation, like high-k gate insulators, FinFets and more..

Been done already

[Snarfvs Maximvs]

Numerical already developed phase-shift mask tech (http://www.siliconstrategies.com/story/OEG2001042 3S0029). Note that they could use 248nm tech to make 25nm features in 2001. Intel apparently licensed it 2 years ago!!!