Bright Peaks for Smaller Chips

Salden writes "University of Wisconsin scientists propose a way to create 20nm chip features. They were investigating the limits of X-ray lithography and discovered that they could control the phase of X-rays by adjusting the gap between a mask and wafer. Pretty cool."

Comments

Ultrasmall chips

[Sunnan]

Just when you think they couldn't get any smaller than those annoying crumbs in the bottom of the bag. Why doesn't anyone make large chips? That would be easier to grab and eat.

Its not just the drawn length that matters

[twfry]

Already with 90nm processes, the height of the trans' gate is ~1.2nm. That's about 5-10 silicon atoms. The net result is you have to continuously lower the operating voltage to reduce current leakage. 90nm processes operate at ~1.0-1.5V.

A drawn 20nm process will have an even shorter gate height. What would we be down to then? ~1-4 silicon atoms? This would force the operating voltatge to be lowered even more, possibly approaching Vt. (I forget exactly but around ~0.7V)

I'm not saying that we'll never have a 20nm process, we will. But there is going to be quite a bit more involved than figuring out how to mask the waffer. i.e. double gates, etc.

Re:Its not just the drawn length that matters

[Anonymous Coward]

you must be talking about high-Vt transistors. because operating speed is crucial, most state-of-the-art transistors have Vts around .3-.4 V.

the smaller transistors will definitely lead to other problems for analog circuits. First of all, short-channel noise increases with maximum voltage decreasing, making it harder to achieve low noise figures.

Re:Its not just the drawn length that matters

[Bender_]

First of all, the parameter you are speaking of is not the "Gate height", but the gate oxide thickness. Dry oxidation allows very thin gate oxides, also below the current mark. Manufacturing these oxides is a comparably easy problem, however decreasing oxide thickness will increase the amount of current tunneling through the gate. This is going to be quite a problem in 65nm and below.

To circumvent these problems there are a multitude of options under investigation, like high-k gate insulators, FinFets and more..

Re:Its not just the drawn length that matters

[Brandon30X]

As the transistor gets smaller, more current will leak throught the thinner gate. One way to fix this is to use a high-k dielectric. This is not easy, the one single greatest thing about silicon that makes it so useful is its natural oxide, silicon dioxide. You basically put the wafer in an oven, and it grows its own dielectric on the surface. High-k dielectrics have to be applied in some way.
-Brandon

Radiation Therapy? Or Spying!?!?

[ackthpt]

They were investigating the limits of X-ray lithography and discovered that they could control the phase of X-rays by adjusting the gap between a mask and wafer.

So when I had 6 weeks of radation therapy they could have been building a chip out of my own tissue to track me! That's all I needed to know. Packing bags for Idaho ASAP

What's next?

[Longjmp]

What I'd be really interested in is what will be next in chip design. At one point traditionally designed chips will be at a single (or a few atoms per transistor) and shielding from natural radiation will be an issue, just as an example.

Even if this wouldn't be an issue (I'm no expert,) there will be a physical limit.

It seems that new designs are overdue. Quantum computers maybe?

Been done already

[Snarfvs Maximvs]

Numerical already developed phase-shift mask tech (http://www.siliconstrategies.com/story/OEG2001042 3S0029). Note that they could use 248nm tech to make 25nm features in 2001. Intel apparently licensed it 2 years ago!!!

Re:Been done already

[waferbuster]

Phase shift masking techniques have been in use for several years, and involve changing the transmissive properties of the reticle/mask material so as to shift the phase of light passing through select portions of the reticle relative to the clear areas. This process is done purely through mask design.

The article involves a totally different concept, in which they are controlling the mask-to-wafer distance so as to control the phase of the light hitting the photoresist. Control of that mask to wafer distance in current technology is not rigidly controlled. It's considered fine to have the reticle in the same rough focal plane as the wafer, but not controlled tightly enough to keep phase polarity intact throughout the exposure field.

It's an interesting technology demonstration, but I'm not convinced that it's adaptable to a manufacturing environment due to the amount of flatness variation on a local exposure field. Wafers may look flat, but on the transistor gate level, it's very lumpy. Sure, some areas of the field will be in phase, but other areas won't be in the correct phase spoiling the chances of getting a working circuit.

It's easy to get a single transistor scaled to incredibly small sizes. It's another matter entirely to get an entire exposure field of consistently small devices, all of which work.

Interesting article...

Re:Moore's Law, anyone?

[Esion Modnar]

And what happens when the smallest chip feature is a single silicon atom? What then? Huh? Huh?