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New PPC/Linux PDA Reference Design From IBM
kinema writes "It looks like IBM has released a new Linux/PowerPC based PDA reference design called e-LAP ("embedded Linux application platform"). It features a PowerPC 405LP, 30MB SDRAM, 32MB NOR Flash, 64MB Disk-On-Chip Flash, 240 x 320 color LCD, Stereo speakers, Microphone, USB (both host and client ports), a 3000 gate Xilinx FPGA, SDIO slot and last but not least a TCPA security chip. I for one would love to see some good PowerPC based PDAs on the market."
Why wouldn't they run a Linux version on it with a regular PC chip and be able to sell the device cheaper?
You mean an x86? They eat too much power to use portably.
There are a couple of low-power x86 compatibles - the Transmeta Crusoe and VIA Epic - but don't know if they're low power enough. Plus they're someone else's technology whereas PowerPC is IBM's own.
Here is the official IBM press release.
Field Programmable Gate Array
I learned a bit about these when I was in college...when set up right, they are much faster than microprocessors, and can be changed on-the-fly by writing new array logic to it.
Future DRM?
That would be the TCPA chip, my friend. Palladium anyone?
llamafresh
I couldn't find a long little dogie, so I got two short ones and spliced 'em...
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Additionally, a plug-in "developer sled" adds the following options, for development and debug purposes . .
USB 1.1 host
10/100 Ethernet
Serial port
8- or 16-bit PCMCIA slot
JTAG debug port
Flash programming port -----
My spirit takes a journey through my mind...
IBM says that the 405LP has good power management features (see link). I tend to agree with them, but also with the parent who says that this won't be the cheap solution for everyone.
The 405LP PR
From http://www.ibm.com/ibm/environment/annual2002/prod uct.shtml:
The first product to emerge from the Low-Power Computing Research Center is the low-power 405LP chip, which enables system software to control and reduce active power by dynamically scaling processor performance to the level required to support the application. Wherever possible, the 405LP offloads processor demands by use of hardware accelerators and aggressively shuts off portions of the device when not in use. Standby power is also reduced. The 405LP includes a mode in which power is reduced virtually to zero while still providing "instant-on" response to an external stimulus, such as a pen stylus on a touch screen.
Read the article. Notice that it mentions that the PowerPC 405LP chip not only contains a PPC 405 core, but a substantial number of other devices. DDR Controller, DMA Controller, LCD Controller.. and a myriad of others important ones. This significantly reduces the number of chips a manufacturer needs to put in a device, with the result of dramatically reduced cost.
Also, anecdotal "PowerPC chips are more expensive" _may_ hold for the PC market, but remember that this is a radically different chip geared for a radically different market (the article mentions a top speed of ~380 MHz!). In reality, IBM has priced this particular chip very reasonably -- wholesale price $100. Those numbers ought to be available soon.
Development of this chip was on Linux right from the beginning, and people were using them around the lab as MP3 players throughout! A great platform for hacking around with.
I think you miss the whole point of the powerPC architecture. The fact of the matter is powerPCs were designed to be extremely scaleable. They are all over the place in systems you would never know. The best example I can think of is the electronic control unit in many cars. It just happens that the powerPCs you hear about the most are Motorola's G4s, IBM's Power970, etc. The whole concept of the powerPC is to have a powerful unified processor "backbone" for anything from a blender to a rackmount server.
I wish there was some there was some way that I could be outside playing basketball, in the rain, and not get wet.
This is a typical artifact of RISC chips. Instructions are fixed size, and usually the same size as the general purpose registers. When you load from an immediate value (a value contained in the instruction), the instruction has insufficient room for a value as wide as the instruction itself after specifying the instruction, the destination operand, etc.
The reference in the post and in the article to a Xilinx XCR3128XL FPGA is incorrect - the XCR3128XL is actually a Xilinx CPLD. While both are reconfigurable, the primary difference between an FPGA and a CPLD is that an FPGA is SRAM based, and must be programmed each time it is turned on, while a CPLD is Flash based, and can keeps its configuration between power cycles. Additionally, FPGAs tend to have more logic and more features.
First Falcon-1 to orbit, then Falcon-9. Then I can die a happy man.
Don't forget that the major market for PowerPCs is embedded devices. One of the reasons Apple has lagged in the MegaHertz war is that Motorolla sells many more embedded CPUs then desktop CPUs. Since users of embedded CPUs generally are more interested in power consumption then speed, you can guess where Motorolla has focused.
XScale is just the ARM compatible processor of Intel. GCC supports it.
It looks to me from the pictures as it the machines is running Trolltech's QTopia palmtop environment, just like the Sharp Zaurus. This is good from at least two points of view. Firstly it means it's easy to port the existing software for the Zaurus, and relatively easy to port KDE and other Qt based apps; and secondly because it means that people producing software for Linux palmtop devices get a wider market with a consistent UI look-and-feel.
I'm old enough to remember when discussions on Slashdot were well informed.