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AMD Moving to a 400MHz Bus?
An anonymous reader writes "According to this tantalizing Infoworld Scoop, AMD soon introduce a 400 Mhz bus. Seems that SiS's big announcement at CEBIT is the SiS748 chipset, which supports both 400 MHz DDR & AGP 8X, and is targeted at the upcoming Athlon 3200+."
No, Intel is not at 800MHz FSBs yet. They are about to move to 200MHz quad pumped, whereas AMD are about to move to 200MHz dual pumped buses.
The problem with the NForce2 is that performance gains with the dual-ddr setup is nullified when you FSB and memory bus become asynchronous. Benchmark it now, and with your memory set to 181/362 and see if it's true in your case as well.
All digital data is synchronized to a clock, be it source-synchronous (i.e. clock comes with data), which is the case with DDR, or recovered clock (i.e. clock information is based on rate of change of incoming data). Whatever scheme you get, you will still have a clock inside at some point.
Traditionally, the memory elements or registers on a chip will ignore incoming data until the clock signal undergoes a positive transition, i.e. logic low to logic high. At that point, assuming the data has been stable for a long enough period of time before and after the clock edge, it will be captured. However, since there is only one positive edge per clock cycle, data can only be captured on that edge.
In a double-pumped scheme, what you have is a set of 2:1 multiplexors that go to two different sets of registers. One is sensitive to positive edges, the other is sensitive to negative edges, i.e. logic high to logic low transitions. If you simply wiggle the data out faster, and you have a double-pumped scheme with a small FIFO buffer, you can recover data twice as fast as a single edged scheme. On the interface itself, there are special low skew low insertion delay clock distribution schemes that enable this to happen without too many problems.
In a quad-pumped scheme, you actually have two separate clocks that are 90 degrees out of phase with each other. In effect, you have two positive and then two negative edges to work with internally now. You wiggle data out at 4x the single data rate, and have 4:1 multiplexers to the registers, plus (again) a careful layout of the internal clocks.
The area overhead in such schemes is minimal (~10% for DDR) and really takes advantage of the speed of on-chip devices. It does take some special consideration, but from the perspective of increased die size, it's not a problem. Power, however, is significantly increased for both I/O (SSTL-2 type stuff) and for core devices because of the data rates, and that is also a consideration during design of not only the power distribution, but also the package/module design and the board design.
And, FYI, Rambus uses multiple serial/deserialization (SERDES) that wiggles data between a pair of signals (positive and negative) whose voltage differential is recovered, not for individual levels, which (supposedly but not actually) simplifies matters. Transmitting data via this differential is actually much faster than a single-ended scheme like DDR currently is (single ended meaning all I/O refer to a common ground (and voltage reference)). Then they even IIRC get into exotic schemes like multi-level differential (i.e. steppings between 0 millivolts differential and full swing). I could be wrong about the latter though...
(http://www.tomshardware.com/business/20030314/ce
Also, every time AMD adds more cache or increases the FSB speed, the processor gets a lower clock rate to product number ratio. The 2700+ with 256Kb of L2 Cache is clocked the same as the 3000+ with 512Kb. So, even if they shipped 3200+'s with a 400 MHz FSB, it would probably be clocked about the same as a 3000+ (at like 2166 MHz). All in all this isn't a bad thing, but you wouldn't be getting an extra 200+'s AND the increase in speed from the faster FSB, the FSB performance bump is figured in to the model number.