Slashdot Mirror


AMD Athlon 64 Performance Preview

k-hell writes "It seems like X-bit Labs have gotten their hands on an 'engineering sample of the AMD Athlon 64 2800+ processor'. Damage at Tech Report is writing that 'This is really fun, but I am a little concerned about their memory latency numbers.'"

8 of 188 comments (clear)

  1. Context Context Context by robbyjo · · Score: 4, Informative

    You should include the full quote of Damage, because just quoting out of context can be misleading. Here's the full paragraph (emphasis is mine):

    This is really fun, but I am a little concerned about their memory latency numbers. They haven't specified what units those numbers are in, but latency numbers come out of programs like cachemem in CPU cycles. Obviously, processors with higher clock speeds will see more clock cycles pass per second than processors with lower clock speeds. One must convert those numbers into comparable units, such as nanoseconds, in order to compare CPUs at different clock speeds. I do expect the Athlon 64 to have low memory access latencies because of its integrated memory controller, but I don't think the gap will be so great as the X-bit numbers would seem to indicate.

    So, the worry is about the units the latency numbers are expressed in. And when you'd see the numbers below, you get an idea why it is so:

    Athlon 64 2800+

    • Mem read speed: 2610.2 MB/s
    • Mem write speed: 1099 MB/s
    • Mem copy speed: 1541.7 MB/s
    • Latency: 96


    Athlon XP 1.6GHz

    • Mem read speed: 1747.8 MB/s
    • Mem write speed: 1156.9 MB/s
    • Mem copy speed: 1244.8 MB/s
    • Latency: 165


    Pentium 4 2.8C

    • Mem read speed: 3193.5 MB/s
    • Mem write speed: 1320.5 MB/s
    • Mem copy speed: 2678.6 MB/s
    • Latency: 260


    See it for yourself.

    --

    --
    Error 500: Internal sig error
    1. Re:Context Context Context by zenyu · · Score: 4, Informative

      Athlon 64 2800+ (true clock 1.6Ghz)
      latency: 96 cycles or 96/1.6 => 60 ns

      Pentium 4 2.8C
      latency: 260 cycles or 260/2.8 => 92 ns

      So there is a 33% improvement, which is cool. (i.e. the P4 is 50% slower)

      The SSE2 instructions were pretty much in equal to the P4 in throughput per cycle, that is as a SEE2 processor it performs like a 1.6Ghz P4... Hopefully they can push the clocks up as fast as Intel has with NetBurst.

  2. Single page view by TeknoHog · · Score: 3, Informative

    Printable version here.

    --
    Escher was the first MC and Giger invented the HR department.
  3. For those who don't follow every AMD move. by WoTG · · Score: 4, Informative

    Remember that this "preview" probably violates one or more NDA's, and it is of a desktop x86-64 chip that is scheduled for September release. In the meantime, it's bigger brother, the Opteron, who has more memory bandwidth, (usually) more cache, and multiple processor support will be released in less than a week (Tuesday to be exact).

    Now the reviews that out in 4 days time should be much more interesting reads. I expect to see someone do a solid x86-32 vs. x86-64 comparison using Linux, maybe other OS's too. And yes, probably even Quake frame rate results. =)

  4. Re:How old is this "'engineering sample"? by Anonymous Coward · · Score: 3, Informative

    The manufacture date shows as 0301 (jan 2003) and copyright applies to the text/picture on the chip not the tech inside.

  5. The two ways of looking at a half-empty glass by vlad_petric · · Score: 4, Informative
    The tests are pretty much showing that an Athlon-64 does not outperform a 32 bit Athlon when running 32 bit apps.

    But here's another way to look at it - Itanium also has an x86 layer, but because it's really just an emulation, its performance sucks.

    So I view this as a huge success. Why ? Because an Athlon-64 will be able to run "legacy" 32 apps at the same speed, while 64 apps will run faster.

    You'd probably wonder why this is the case. Well, IMNSHO it's not because of the wider registers/ALUs, etc, but because of other improvements to the Instruction Set Architecture, like the 8 extra registers (16 total). Because you only have 8 registers on a regular x86, compilers can register-allocate very little. Adding 8 more registers means that you can keep more stuff in the register file, and you don't have to go to the stack (data cache) every single time.

    --

    The Raven

  6. Re:Check out date on processor. by rabidcow · · Score: 4, Informative

    The one that I'm looking at is 0301 (2nd line of numbers/letters) which I will guess to be 1st week 2003.

    Exactly, date codes on chips, which tell you the date of manufacture, are usually 4 digits: two digits for the year, then two digits for the week in that year.

    If you RTFA (as opposed to just looking at the pretty pictures), they say, right under that image: "The production date in the next line of the marking indicates the beginning of this year."

    This is pretty standard, I can pull out my old 8088 MB and read the date code off the processor: 8937 (1989, 37th week) You can find similar date codes on most chips and PCBs. (eg, that 8088 MB has 8945 printed on the back)

  7. Re:3DNow!: Cause of Slow Clock Frequency in InnerC by RzUpAnmsCwrds · · Score: 3, Informative

    3DNow! is essentially a subset of SSE. Removing it would not save a signifigant number of transistors.