Apple Hardware VP Defends Benchmarks

Greg Joswiak, vice president of hardware product marketing at Apple, in a phone interview today, defended Apple's performance claims for its upcoming Power Mac G5, after they came under fire in the wake of yesterday's announcement. Read on for the details. Joswiak went over the points in turn, but first said that they set out from the beginning to do a fair and even comparison, which is why they used an independent lab and provided full disclosure of the methods used in the tests, which would be "a silly way to do things" if Apple were intending to be deceptive.

He said Veritest used gcc for both platforms, instead of Intel's compiler, simply because the benchmarks measure two things at the same time: compiler, and hardware. To test the hardware alone, you must normalize the compiler out of the equation -- using the same version and similar settings -- and, if anything, Joswiak said, gcc has been available on the Intel platform for a lot longer and is more optimized for Intel than for PowerPC.

He conceded readily that the Dell numbers would be higher with the Intel compiler, but that the Apple numbers could be higher with a different compiler too.

Joswiak added that in the Intel modifications for the tests, they chose the option that provided higher scores for the Intel machine, not lower. The scores were higher under Linux than under Windows, and in the rate test, the scores were higher with hyperthreading disabled than enabled. He also said they would be happy to do the tests on Windows and with hyperthreading enabled, if people wanted it, as it would only make the G5 look better.

In the G5 modifications, they were made because shipping systems will have those options available. For example, memory read bypass was turned on, for even though it is not on by default in the tested prototypes, it will be on by default for the shipping systems. Software-based prefetching was turned off and a high-performance malloc was used because those options will be available on the shipping systems (Joswiak did not know whether this malloc, which is faster but less memory efficient, will be the default in the shipping systems).

As to not using SSE2, Joswiak said they enabled the correct flags for it, as documented on the gcc web site, so that SSE2 was enabled (the Veritest report lists the options used for each test, which appears to include the appropriate flags).

Comments

Punish!

[blackmonday]

The one thing he didn't mention was that during the benchmarks, the G5's were also parallel processing computations on the most painful wretched hideous punishments, to be bestowed upon the web server admin who fucked up and released the G5 specs days too early.
The numbers are coming in, and it won't be pretty.

Re:Real world tests

[dspisak]

"To put it in perspective, this is like comparing Intel's Prescott processor (aka Pentium 5 - 90nm) or Madison to G4"

Care to give me a hit off your crack pipe?

The G4 processor has been out in various speed grades and minor revisions for a HELL of a lot longer then the last three months.

The G5 might not be shipping *right now this very moment* but it does physically exist in a stable enough form for Apple to feed confident to benchmark it against known, released CPU technology that is at the leading edge of the Intel workstation performance market.

Sure, Intel is coming out with the Prescott (aka Pentium 4?/5?) in Q4 of 2004 at a speed of around 3.4GHz but that is a *desktop* CPU and not a server Xeon CPU. Intel does have a roadmap spelling out when Xeons get to 3.2GHz and 800Mhz FSB finally.

If Intel has a Prescott system or a more advanced Xeon DP system working well enough to SPECmark I will garuarntee you that there will be a press release from Intel regarding how their "new Xeon 3.2GHz with 800Mhz FSB and expanded cache" now "regains the performance crown back from the clutches of Apple" and expect to see it between now and August when the G5 are expected/hoped to start shipping in volume.