Analysis: x86 Vs PPC

Gentu writes "Nicholas Blachford (engineer of the PPC-based PEGASOS Platform) wrote a long and detailed article, comparing the PPC and the x86 architectures on a number of levels: performance, Vector processing and Power Consumption differences, architectural differences, RISC Vs CISC and more. The article is up-to-date and so it takes the G5 into account too."

Comments

An interesting viewpoint

[downix]

From my experience with RISC CPU's is that rating them by Mhz is often times the way to not understand what makes a RISC a RISC and a CISC a CISC.

Let me explain by example.

My MIPS R4400, running at around 120Mhz, I believe, runs circles around my Duron 750Mhz machine here. This is while the R4400 uses sDRAM vs DDR-RAM in the Duron, and the R4400 uses older plain-jane IDE while my Duron runs ATA-100.

I find it nice to boot up my old Indigo2 and play around, it responds so nicely, and renders quite well.

Re:An interesting viewpoint

[uradu]

> rating them by Mhz is often times the way to
> not understand what makes a RISC a RISC

What you mean is that you can't compare RISC MHz to CISC MHz--or any design's MHz to any other design's MHz, for that matter. Your statement in fact reveals that YOU don't understand RISC, because MHz are a much more reliable metric for RISC than for CISC CPUs. That is because by the very definition RISC CPUs tend to take a constant amount of ticks per instruction, which is not the case for CISC. So yes, comparing two RISC CPUs that both execute one instruction every two cycles on a MHz basis will give you a pretty good comparison of their relative performance.

Re:how long can x86 go?

[Elwood P Dowd]

You could say that right now, "The x86 is not dead, because the RISC processors that replace them have a CISC compatibility layer".

The P4 decodes the larger, more complex x86 instructions into smaller chunks for use inside the processor, which is more or less RISC in its core. The CISC vs. RISC debate is kindof over, because both CISC and RISC chips have been adapted to gain the advantages of each others' design principles. Even the PPC 970 has to decode some of its "RISC" instructions into separate micro-instructions for execution.

The only chip design methodology that still has its original meaning is VLIW. That original meaning is "bankruptcy."

970 is a real superscaler

[norwoodites]

the 970 can have more than 200 instructions in flight at the same time, it can finish up to 5 instructions each clock (4 if there is no branches).

Check your facts, please; G5 IS low power

[LionMage]

Each g5 dissipates a whopping 97 watts

No, two G5 (PowerPC 970) processors together dissipate 97 Watts. Each individual processor dissipates about half that.

Don't believe me? Check out this chart on ArsTechnica. (The heading for the chart reads "Preliminaries: die size, power consumption, and clock speed.") A single 1.8 GHz PowerPC 970 dissipates 42 Watts. So a single 2.0 GHz PowerPC 970 dissipates a little more than that; therefore, it's reasonable that two of them would dissipate somewhere between 90 and 100 Watts, total.

The EE Times article you cited is highly inaccurate. They only look at the total number of fans in the G5 machine, and forget the fact that these are low-RPM fans and are software controlled per-zone to regulate temperature. Low RPM means less volume of air moved per unit time. So the design tradeoff that was made, clearly, is to have more fans running slower in order to keep noise levels down and to target cooling for each zone appropriately.

This is why it's a good idea to check multiple sources for your facts. Then again, if your goal was to present a very distorted version of reality to fit your goal of painting the G5 as a power hungry monster, you would very carefully choose your source of information so that it seems to support your assertion.