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Watercooling Drifting Mainstream
pacc writes "With Prescott said to dissipate 103 W and the dual Apple G5 playing in the same league, air cooling seems less than sensible.
Nikkei Electronics has an article about watercoolers getting standardized by Hitachi. A technology pioneered by a NEC desktop last May."
The 103W figure for the Prescott 3.6Ghz is actually the Thermal Design Power. This is the amount of power the processor is expected to use during "normal" operation. A P4-C 3.0Ghz with HyperThreading has a TDP of about 80W, with an actual maximum power usage of 104W. Assuming a similar scale, a Prescott 3.6Ghz can be expected to dissipate around 130W. It's this maximum figure that really matters, since I don't think most people want their processor to throttle during gaming or whenever they are driving their CPU hard.
Learn more, it is facinating. Look around the old articles on HardOCP and Overclockers.com and you can find out a ton. Just search google! Also, if you look at like the HardOCP forums under cooling, you can find tons of pics of people's Watercooled PCs.
Comment forecast: Bits of genius surrounded by a sea of mediocrity.
The benefit of water comes from several aspects: 1) High thermal capacity - as you said, acts like an energy buffer. 2) Higher thermal conductivity than air - allows heat energy to be transferred faster. 3) Allows radiator (YES! you need a way of dissipating heat) to be located remotely from the CPU. This means you can have a much larger radiator, with far more surface area and airflow than would be possible with a CPU mounted heatsink. Remember, water is just a transport mechanism - ultimately the heat has to escape to the air. If you build the radiator large enough, the temps will be lower than you could practicalally achieve with standard air cooling.
Since when is 43 watts @ 1.8ghz, (I don't think they ever released the 2Ghz G5's power dissipation number, did they?) in the same league as 103watts?
While it puts out a bit more heat than the G3s and G4s mac users are used to, the G5 is still nowhere near as bad as prescott.
The prescott puts out more than doubble the heat.
"The worst tyrannies were the ones where a governance required its own logic on every embedded node." - Vernor Vinge
To join in with the peanut gallery: it's not a radiator, it's a heater core. OTOH, it's larger than the radiator on many motorcycles, is constructed the same way, and does a similar job.
The guy did some great work, but the English wheel to make a simple curve was big time overkill. English wheels are used to make compound curves, usually.
As far as the 'last' great love affair with speed and power being the automobile, America's love for speedy and powerful autos is as strong as it ever was. Fast computers are barely a glint in the eye for the average person. Hell, even most geeks who really make it buy rather nice cars (ask John Romero). And the lowly Dodge Neon is quicker than most average Dodge musclecars of the late 60's, with superior economy and handling. Only seriously high end race only cars back in the day would stand a chance at hanging with something as relatively mundane as a Subaru WRX. Maybe a Yenko or other tuner car could beat them, but then you have to let me mention tuner Corvette's and Mercury sedans. Trust me, *this* is the golden age of the American auto, despite the prevalence of SUVs and trucks (which are quicker, safer, more fuel efficient, more powerful, and more durable than their brethern 'back in the day'.)
While I'm wound up, let me tell you why emacs rulez, and vi is teh suxx0r...
Jesus was all right but his disciples were thick and ordinary. -John Lennon
For the benefit of other readers - Heat pipes are a completely different animal to the water cooling we're talkign about, though they have far greater potential.
Essentially, they're an evacuated pipe with some working fluid injected. This could be water, butane, ammonia or sodium (high temps). Because of the vacuumn, some of the liquid evaporates until equilibrium is reached.
So, we have a liquid/vapor environment. Add heat at one end and local equilibrium shifts, vaporising more liquid. Cool the other end, and local equilibrium goes the other way. The pressure diffence causes the vapor to travel at the speed of sound from one end to the other, whilst the liquid flows back the other way via gravity or wicking.
This leaves you with a device that is 1000 times more conductive than copper of the same dimensions. CPU one end, heatsink/radiator at the other, and there you go!
And about the only way to do this without sacrificing clockrate is by going to a smaller fabrication process.
Sorry, that's commonly believed, but wrong. There are lots of ways to reduce power consumption. Reducing gate widths (0.25um -> 0.13um -> 90nm) is commonly touted as a good way to reduce power, but in most cases that's more marketing pitch than reality.
First, there are two types of chip power to worry about (1) leakage, which happens all the time, just by being on, and which used to be always much much lower than (2) the switching power, or maximum dissipation when as many transistors as possible can switch at once (which, BTW, can never be all of them, and it's really, really hard to find the stimulus that makes maximum power happen. So, esitmates like the ones in the article for peak power are often made assuming a somewhat-arbitrary switching factor that may be low or high).
As gate sizes shrink, the effective capacitance of the gate shrinks, and voltage can be lowered (to a point). Capacitance varies with gate area and inversely with distance between "plates" of the gate (C = k*A / d). Reducing the gate width (space between the plates) actually increases capacitance, and this itself would increase power. But, you're also able to reduce the gate area (though not as much, but in 2-dimensions, so shrinking gates is usually a reduction in C). Most importantly, you can decrease voltage, since power varies with the square of voltage, this has much more impact on power than reducing gate capacitance (size). When we went from 0.25um (3.3V)to 0.13um (1.5V), we got a nice fat 1.8V drop in voltage. But 0.13um is 1.5V too, or 1.3V at best, and I've never heard of a 90nm (0.09um) process under 1.1V. The V isn't dropping as fast any more because the noise margins are getting too small.
Since p(switching) = 1/2*F*C*V^2 (F = clock freqyency, C = capacitance, and V = max voltage, lowering C (and moreso V which we can reduce some, but not much below 1.0V so far) will lower power a bit. Linearly with C. But unless we can reduce V, reducing C much more won't help a lot because we have more total C's (transistor gates) on the die, because they are smaller we can fit more.
But now, at 0.13um, and more at 90nm, it's not the switching power, but the leakage (always there) power that's getting worrisome. It used to be 1/20th of switching power or less, but now the gates are so small current of the same order of magnitude (almost) of switching leaks all the time.
So, the more you shrink, the more you have constant power, which is harder to deal with since you can't throttle it, and it's always cranking out. Worse yet, the more you shrink, the more gates you can fit on one tiny little die (the feasible mfg'able die size stays around 17-18mm max regardless of gate size once the process matures a bit, but bigger dice have ridiculous failure rates and thus silly high prices). And the gates shrink in 2 dimensions (L and W), so you get a squaring increase of the toal gate count, and only a linear decrease with C. Shrinking gates to save power doesn't work.
So, if we can't keep shrinking to save power, how can we? Lot's of ways. There are dozens of EDA companies with power-minded RTL coding, synthesis, and even place and route tools ready to help you reduce your power if you have a few $100k/seat/year. Or, you could use a SSC (Spread-spectrum Clock, where each clock edge is off by a bit to reduce power, but it slows down the max clock rate a bit too, of course). You can also try to use beneficial clock skew to reduce power after timing closure, or gate the hell out of all the clocks and only enable what you need (a la mobile chips). Or switch to asynchronous, or self-clocked design (every thing has it's own clock, which sends a clock to the next thing, etc. -- it's HARD to design!). Anyway you look at it, it's a hard problem. And people who
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