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Introducing Probability into Chip Design
prostoalex writes "The August issue of Intel Developer Update has an interview with Shekhar Borkar, Intel Fellow and Director of Circuit Research at Intel Corp. talking about the future of microprocessor design and what goes on inside Intel Labs. Borkar tells why we need even faster processors and how probability will make its way into future chip designs - "It's like the shift from Newtonian mechanics to quantum mechanics. We will shift from the deterministic designs of today to probabilistic and statistical designs of the future.""
Sorry could not resist.
UM, Ford. theres an infinite number of monkeys outside that want to talk to us about a script for hamlet they've hammered out. PROBABILITY FACTOR OF 1 to 1: any other problems are your own lookout.
...back in the heady days of Concurrent Computer their top-of-the-line 3280 processor has "usual branch" instructions. The compiler could use the usual branch instructions to provide hints about the probability of the branch being taken to the processor. In a loop, for instance, you'd use a "usual branch not equal" (UBNE) instruction to send execution back to the top. This would indicate to the processor that it should preemptively invalidaate the cache and pipeline.
I'm sure many mainstream processors have this now, but it's funny to think that CCUR had this technology in the late 1980's.
Tiller's Rule: Never use a word in written form that you've only heard and never read. You will end up looking foolish.
In the interview, a lot of things have been left out. The topic is first and foremost old. It goes back to the 80s. Statistical variations have always been taken into account by using worst cases. Problem is that the worst case approach sucks in the latest technologies, so more sophisticated methods have to be used. There has been a lot of research in the last 10 years (Check american, german, and italian universities, just to name few).
Also, the problem is old, meaning that analog designers had to deal with these problems since the early stages (example: the offset in the operational amplifiers is caused by transistor performance mismatch). Now, digital designs are affected too. First on the clocking network and now all the rest. Furthermore, it is widely known (in the community) that interconnect variations are of the same order of magnitude of the device (i.e. transistor)performance variations, and on the top of that dynamic effects (like cross talk) may severely affect the performance.
I don't agree with him on the fact that all the variations are gaussian, there is plenty of literature that states the contrary, and major chip makers know it very well.
Last but not least, there are already tools that deal with statistical variations, although none of them can handle a microprocessor, as they are mostly circtuit simulation-based. All in all, the good news is that awareness is spreading thru the designers.