Transmeta Founder Talks Chips

gManZboy writes "Dave Ditzel, CTO and Founder of Transmeta (you remember Transmeta? weren't they supposed to kick some Intel booty?) sits down and speaks with Alpha and StrongARM chip designer Dan Dobberpuhl about the history of CPUs, where they're heading, and how the heck we'll keep up Moore's Law (if we can)."

Comments

Flash, I wish, give me a break

[fnj]

The hard drive ... can ... be [replaced by] a ... flash disk [holding] 8 [GB}.

(1) You need more like 80-200GB to replace hard disk these days.

(2) Flash is appallingly slow writing and does not seem to be getting much faster anytime soon.

The hard disk is a moving target, and flash is not catching up.

Re:total energy available

[bartash]

Was it this or this or this perhaps?

did you rtfa?

[glassesmonkey]

Not that you did read the article, but here's a great paper (pdf) on low-power processor design with lots of graphs and equations showing where the architecture can tradeoff power to keep your silicon chips from melting.

The paper is out of Stanford paid for by your tax dollars.. Hopefully you won't notice the part about the address at Stanford University being the William Gates Computer Science Bldg

Re:total energy available

[glassesmonkey]

no, not that I saw in those. But this pdf html does have the graph showing how the WW 500M CPUs are currently using the power output of 4 Hover Dams (9000 MW) and a nice exponential graph.

Re:"kick some Intel booty"

[Anonymous Coward]

It's amazing how the MHz Myth continues to this day.

Let me say it once again, it does equate to performance. If you still believe it does I will gladly trade you this nice new 3Ghz Celeron for your 1800Mhz Athlon64.

Re:Translator code...

[Fnord]

Sigh, this comes up every time someone mentions transmeta. Yes the "translator code" (its acually called Code Morphing) is cool. Yes it takes x86 and converts it to the crusoe's native instruction set which is actually a 4 way vliw processor. No that was not done to run multiple instruction sets. That was done so that some of the complexity of the chip was done in software instead of silicon, making the chip smaller and less power hungry. In fact they've repeatedly said that while its theoretically possible to code morph other instruction sets, they've designed the underlying, real instruction set to effectivly run x86 code. Just in a simple and more efficient manner. The whole hype about multiple instruction sets was from people speculating about what could be done with this cool new code morphing thing, and then others looking at the comments assuming it was already planned. Transmeta themselves never contributed to that hype in the slightest.

Re:Fabs would limit their projections severely

[stevesliva]

I think you misunderstand the connections between the tools within a fab and the fab itself. The processes used to manufacture chips within fabs are constantly evolving within the same physical plant. In addition to not necessarily being obseleted due to process shrinks, one fab can produce several different process variations, even within a given node. No fab is limited to, for instance, a 130nm SOI 7-level metal Low-K process. In the article they speculate about SOI (silicon on insulator) like it's some far-out concept, when it's probably used in the PPC970 processor in the Mac G5. IBM's big on SOI, while Intel has been against it. But that doesn't mean IBM's fabs can only make SOI wafers. SOI isn't well suited for every application.

New fab construction is often driven by factors unrelated to process. Increased wafer starts, materials handling for 300mm instead of 200mm wafers, bigger/smaller floorplan, different cleanroom specs, etc.