NVRAM With Disordered Assemblies (Smaller/Cheaper)

chadjg writes " Jim Tour, of Rice University says "Our research shows that ordered precision isn't a prerequisite for computing. It is possible to make memory circuits out of disordered systems." The article on www.e4engineering.com says the team has made "NanoCells", self assembled devices made from gold nanowires and organic conductive molecules. These NanoCells are the first devices of their kind to be made into working microelectronic devices, apparently." Yep. Let an untold number of machines try to create NanoCells, and statistics says you'll find the most efficient kind.

Comments

Re: Just a thought...

[Black Parrot]

> Is this a step towards creating quantum-effect neural networks (i.e., thinking machines)?

No, it's just a memory technology.

Well I predict....

[donscarletti]

My prediction is that you didn't actually read it yourself.

This is because if you did, you would realise that it was very well written and not hugely technical. I wouldn't be supprised if 95%+ of the slashdot crowd did understand it.

As a general rule, slashdotters seem to get very zealous and have a habit of not RTFAing, but they generally have good comprehension skills and I don't think you give them the credit they deserve.

Predicted density in large scale devices?

[G4from128k]

The article lacks useful information on the expected density of the circuits in large-scale applications. On the one hand, the nano nature of the device would seem to permit tremendous density that far exceeds anything that can be fabricated with masks and etching. On the other hand, two major major problems would limit the practical density of memory cells in usefully large dies.

1) I would expect these devices to have a very large fraction of unusable cells. A fair percentage of nanocells would probably be fixed live (always storing a 1), fixed dead (always storing a 0), leaky (decaying faster than the nominal refresh time), or disconnected. The percentage of writable, readable, nonvolatile, connected cells might be very low. This makes the effect density (and effective memory cell size) much worse than the nanoscale of the process would lead one to expect.

2) The reach of the disordered connections into the field of nanocells would be limited in distance. I would bet that the disordered wires cannot be made to reach very far from the edge. Phenomena like wire-to-wire disconnects, wire-to-wire shorts, wire-to-substrate shorts, accumulated resistance, accumulated leakage would limit how far from the edge we can access the field of nanocells. Note that the experimental cell is only 10 microns by 40 microns. Can this technology be scaled to a 1000 micron x 1000 micron die or bigger? Even if the density is extremely high, the inability to scale to size might mean that all we can do is an extremely small 64 kilobit device. Of course, this might be solvable with clever overlays (like a mesh of traditionally fabricated conductors) that let us create macroscopic nanoRAM dies that have scale-limited microscopic nanocell field areas. The statistics of interconnections (or percolation theory) can help us determine the scalability of the concept.

I'm not suggesting we abandon nanocell technology, only that we consider the scaling effects when trying to predict whether this nanocell technology has the potential to revial existing technologies. Moreover, the existing semiconductor technologies are a moving target. By the time nanocells reach the market, we might have 3 nanometer semiconductor circuits using gamma-ray free-electron lasers and vertical ion implantion in a diamond substrate (or something). Future semiconductor densities might makes the nanocell density not that competative.