A History of PowerPC

A reader writes: "There's a article about chipmaking at IBM up at DeveloperWorks. While IBM-centric, it talks a lot about the PowerPC, but really dwells on the common ancestory of IBM 801" Interesting article, especially for people interested in chips and chip design.

Comments

Obligatory Quote of the Day

[crumbz]

"Finally, the Fishkill operation is so hip that the server room runs exclusively on Linux."

I didn't think it was possible to use the words "Fishkill" and "hip" in the same sentence with a straight face.

One of the coolest things about PowerPC chips

[Anonymous Coward]

Is its revolutionary three level cache architecture, utilising a 3-way 7 set-transitive cache structure, which gives performance equivalent to a 2-level traditional x86 style cache for more content addressable memory. Each processor has a direct triple-beat burstless fly-by cache gate interface capable of fourteen sequential memory write cycles, including read/write-back and speculative write-thru on both the instruction and data caches. Instruction post-fetch, get-post, roll-forward and cipher3 registers further enhance instruction cache design, and integrated bus snooping guarantees cache coherency on all power PC devices with software intervention. Special cache control and instructions were necessary to control this revolutionary design, such as 'sync', which flushes the cache, and the ever-popular 'exeio' memory fence-case instruction, named after the line in the popular nursery rhyme.