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IBM Plans Collaboration On Power Architecture
TheInternet writes "According to CNET News, IBM has made a series of announcements regarding the opening-up of the Power chip architecture. The story lacks technical details, but apparently, IBM is going to divulge more information about Power/PowerPC, and expects collaboration from the industry on the future of the chip. Nick Donofrio is quoted as saying: 'We will free electronics manufacturers from the limitations of proprietary microprocessor architectures', and Red Hat and Sony are two companies listed as taking part. Power5 was also shown, as was the Blue Gene/L supercomputer, using 32 500MHz processors to achieve 128 gigaflops."
Anyone else think this on the first read?
Does this sound like a possible good contender for a general purpose replacement for x86 as an "Open CPU" that would work well with F/OSS apps? One that can't be tied down with DRM in such a way that only large megacorps (I won't name them, except to call them "Microsoft" and "Intel". Oh hell I named them whoops) can end up defining what may or may not run?
I've read the general slashdot crowd clamoring for something like this that's free from central control. Does this look likely to you? Would it be a benefit if it did come about?
There are sound business reasons for all the big-headline stuff IBM's been doing lately, but I think they're doing it because it's the biggest, best, and cheapest PR anyone's ever heard of.
Sure they're positioning POWER/PowerPC as the only architechture that can challenge x86 in a meaningful way. Sure if they release enough of the firmware and stuff it'll probably be better for some open source stuff than x86 is. Sure they're a services company and this will put them on the back end of even more stuff.
But honestly. Everyone loves them. That's what they really need if they want to entrench themselves everywhere.
I rarely criticize things I don't care about.
Umm, the instruction set is documented and everything. There's this PDF you can download.
The problems with emulators have to do with RISC vs CISC differences and register-rich vs register-poor architectures. I have to go, so I'm not going to go into the details here, but the general idea is this: for the specific case of emulation, it's easier to write an emulator if your host architecture is more RISCy than your emulated architecture, and it's easier to write an emulator if your host architecture has more registers than your emulated architecture.
The PowerPC has a very cluttered instruction set, but it still basically follows RISC as a philosophy-- you're still in a situation where instructions from other architectures have mostly instructions that can be broken down efficiently into a series of PowerPC instructions. Which means that efficiently assembling series' of PowerPC instructions into single instructions while emulating on more CISCy platforms is kind of hard. The PowerPC also has a whole lot of registers, and they're all general purpose so you can't play neat optimization tricks as easily as you can when emulating the Intel x86. Meanwhile, the architecture you probably want to do this emulation on-- x86-- is shit for registers.
The PPC emulation problem has to do with unfortunate conflicts between design philosophies and emulation perverse cases more than anything else.
-- Super Ugly Ultraman
That Blue Gene/L machine being shown is only a small part of the full machine they are building for LLNL. When its complete, IBM estimates that it will run at 360 TFLOPS, at a fraction of the size and power consumption of the current #1 supercomputer. Even if they miss the mark by 50% it represents a fairly significant leap in processing and power consumption. And hey, since it will only occupy 64 racks, you can just about fit one in your garage! (Nuclear reactor to power it not included...)