Intel Plans for Dual-Core Prescott CPUs in 2005
scapermoya writes "X-Bit Labs is reporting that Intel is planning to step up their introduction of dual-core processors, with the first chips to hit the market in late 2005. Intel announced this plan at the Technology for Business Today seminar, held in Washington, D.C. Looks like NetBurst is sticking around, despite what we have heard lately about a move toward the 'M' architecture. Supposedly, thanks to HyperThreading, the OS will see 4 installed processors. Snazzy."
Isn't it a llittle soon to claim to put 4 processors in one chip by 2005, especially sinse last I had heard, one processor was causing a heat concern. Have they fixed this or is this Intel making predictions and setting dates that will only get pushed back anyway?
The stupidity of your average American is just about the same as the average European, we simply show it off better.
I remember when Hyperthreading came out there were serious performance problems in many apps. This lead many reviews and I must assume educated consumers to disable this feature.
Other than tollerance for spyware does this have any real advantages?
Didn't we hear some rumblings on this count from AMD? When does their roadmap state this stuff'll be ready to go?
Worst. Trol. Evar.
Because intel's always so reticent in giving out the instruction sets and specs for their processors. That'd be a really smart business move, and the #1 way to attract developers.
Send lawyers, guns, and money!
1 processor core technology is causing heat consernes in thin core. The point is as the core gets thinner the power required to stop lekage across a ever thinner insulation layer increses. A couple of jumps thinner and we would have chips that require the power of a houshold iron. Multi-core is a solution to this problem, maybe Intel are not using very thin core technology to reduce heat in there multi-core processors. There was a very interesting article about this in New Scientist but I dont think it was one they put on the web for free ;-(. (sorry I posted this as a reply to someone elses article but am hanging it of the original post as it seems relevent).
Lot's of their old ones, all the ones I needed, are free and available in PDF format.
All those moments will be lost in time, like tears in rain.
The Itanium goes in the opposite direction, requiring the compiler to explicitly parallelise instructions. While this approach has the potential to allow much more scalability, it requires a much cleverer compiler. The combination of EPIC/VLIW chips with JIT compilation and run-time profiling could create some very high speed applications.
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I'd take a DUAL dual-core 2.5GHz G5 powermac over a dual single-core 3GHz anytime.
It would probably be less of a technical challenge as well, and would follow the "GHz doesn't matter" philosophy the POWER(tm) manager said a few days ago.
The 90nm process encounters problems at high clock speeds. So, bring on more efficiency at lower clock speeds!
Ask them for the specifics of their new EFI "BIOS" so you can work with it.
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