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AMD Going Dual-Core In 2005
gr8_phk writes "We recently learned of Intel's
plans to go dual-core in late 2005. Well it seems AMD has
decided to follow suit. It should be noted that the K8 architecture has had this designed in
from the start. Will this be socket 939 or should I try to hold out another year to buy?"
you can find them all here. It seems news has gotten around, and that AMD's dual core will consume just about as much power as a single core CPU at 90nm.
ignorance is bliss. googlefiberatx.com
heat
Yes..the evil of all machines
the reason why when the AC is not on in my house, and it is 90degrees outside, my computer resets
and of course..the reason why we're not going quad core
well..at least that's my personal opinion...as for the real reason...probally for profit...
Moore's Law has NOTHING to do with CPU speed.
/morz law/ prov. The observation that the logic density of silicon integrated circuits has closely followed the curve (bits per square inch) = 2^(t - 1962) where t is time in years; that is, the amount of information storable on a given amount of silicon has roughly doubled every year since the technology was invented. This relation, first uttered in 1964 by semiconductor engineer Gordon Moore (who co-founded Intel four years later) held until the late 1970s, at which point the doubling period slowed to 18 months. The doubling period remained at that value through time of writing (late 1999). Moore's Law is apparently self-fulfilling. The implication is that somebody, somewhere is going to be able to build a better chip than you if you rest on your laurels, so you'd better start pushing hard on the problem. See also
from a google search.
Moore's Law
actually there is plenty of bandwidth left in hypertransport to pull it off. also each cpu gets its own bank of memory. the design is superior to all others for SMP. even AMD's man CPU man says that at infoworld
AMD's dual-core server processors will share a single memory controller, Weber said. This won't create a bottleneck because a server with two Opteron chips, and therefore two memory controllers, already has more than enough memory bandwidth required to run that system, he said.
"It's always a juggling act to add a little more processing and a little more memory. Right now, we have plenty of memory and I/O bandwidth, so we're adding processing," Weber said.
The dual-core chips will work with current socket technology in motherboards that are rated for the specifications of the dual-core chips, Weber said. A BIOS change will be required, but otherwise the chips will work in the same sockets as single-core Opterons, he said.
ignorance is bliss. googlefiberatx.com
SMT is only needed if your execution units are having trouble remaining filled up, which was the problem with the NetBurst architecture due to the huge hits that it takes with a branch mis-prediction penalty. When a mis-predict happens the execution unit has to sit idling away and wait for the proper info to go be re-fetched. With SMT, the unit simply switches over to one of the other threads waiting in the wings which keeps the processor doing useful work instead of wasting cycles. This is why the software has to be re-written to take advantage of it so that the processor knows which threads to give priority to.
Intel stuck SMT into the Pentium in order to balance out the some of the negative effects the go hand-in-hand with a processor that has a LONG pipeline. AMD has a much shorter pipeline (especially when compared to the new Prescott) and therefore they don't suffer much of a penalty when a mis-predict happens. Also, if I remember correctly the Athlon was already known being extremely efficient in terms of resource allocation within the processor since AMD can't afford to just dump tons of extra cache onto the chip.
Both of these things taken together means that using up extra real estate on the die of the Athlon in order to get SMT isn't really worth it in terms of the performance it would bring. Even on the Pentium the benefits aren't all that hot and it's only in specific types of code that you see any impresive speed gains.
The opteron (k8) has an integrated memory controller and up to three hypertransport links. In a dual k8 system, the cpus communicate over a single hypertransport link and are usually paired with their own memory bank. If one cpu needs data from the other's bank, it comes over the hypertransport link. Some cheap dual opteron boards save traces by pairing one cpu with all the memory banks - so every memory operation on the non directly linked cpu passes over the h-link.
The dual core cpu might have the pins for two seperate memory bank arrays or just the pins for one. Either way, the situation as far as dual k8s go is not really different from what we have already. Either way, it's a few steps above the p4 design: shared cpu bus to northbridge to memory. (yech! with a single proc, this introduces latency, with multiproc, you get contention and latency at every level)
AMD's cpu interconnect is so well thought out... it gives me the warm fuzzies pondering it:
A uniproc hammer needs one h-link for io.
A dually needs two per core: 1 for core to core, 1 for io (though all the io on all the boards I have seen feeds to only one proc's h-link... so that you don't lose PCI busses and such if you have only one proc installed, I suppose).
Quad and above requires three: each core links to two other cores, leaving one h-link per core for io. One could have a pci-e bus per proc, if one desired. But again, I haven't seen a design that doesn't feed all io into a single h-link.
Since no one uses the extra h-link anyway, a dual core package for a dual core system would need only one external h-link (saving some cash).
A quad core, dual package system would require three h-links feeding out of each package, though. But even then, the number of h-links laid out on the mobo is reduced and the whole shebang should be cheaper.
Intel's "one huge shared bus" + northbridge design is definitely being trampled...