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MRAM Inches Towards Prime Time
levin writes "According to an article over at EETimes, magnetoresistive RAM chips are getting a little more practical. Infineon Technologies released info on a new 16M MRAM component on Tuesday and the read and write cycle times of this chip make it 'competitive with established DRAM.' How long before nonvolatile memory becomes the solution to crash-prone software rather than better programming?"
How long before nonvolatile memory becomes the solution to crash-prone software rather than better programming?
What? A crash-prone program is a crash-prone program, regardless of whether it vanishes or not when you turn the power off.
However, there are 8 to 16 chips on a DIMM. So, multiply by 8 to get 16MB for a single-sided DIMM, or 16 to get 32MB for a double-sided DIMM. Not good, but for a new memory type, it's catching up quick.
No shit. I wonder what kind of havok a shitty OS will wreak on an NVRAM system? I hope there is always a way to reset the banks, because I don't trust much of anything, especially Windows, to behave well enough to stay "running" like that with no "failsafe" power-cycle option.
Slashdot is proof that Sturgeon's Law applies to mankind.
No need for something so complex. All one has to do to recover from such a state is to extend (or emulate one of volatile RAM's 'features', if you wish) the 'reset'-function:
The moment you push the 'reset' button, not only does the system reboot, but the memory is also wiped, after which a non-corrupted copy is loaded from the 'HDD' (or whatever is used for storage).
So in other words, the 'power'-button would be used to power the system down, while the entire state would be preserved (like the hibernate feature).
The 'reset'-button would literally reset the system to its default state, just like when you boot a system employing volatile RAM.
Site & blog: http://www.mayaposch.com
No, that's wrong. The truth is that errors in dynamic RAM can be introduced on each refresh. As you said yourself, dynamic RAM needs to be refreshed every few milliseconds--read and rewritten. Each time that happens, it's possible for an error to be introduced. If the refresh circuitry reads the value incorrectly, you get an error. If it writes the value incorrectly, you get an error. The longer the RAM sits around, the more refresh cycles, so the greater the chance for errors. If the voltages aren't stable enough, for example, you'll find a "1" bit refreshed with slightly too low of a current so that when the next refresh comes around, it's read as a "0" as it's been discharging over time and falls just below the threshhold to be read as a "1".
As far as errors not being introduced when the memory is "idle," you're thinking of static RAM. Static RAM doesn't need to be refreshed, and thus actually CAN be idle. So it holds a huge advantage here. Without the refresh cycle, there's no place for errors to be introduced except during the actual reads and writes by the processor.
One of the interesting aspects of MRAM is the ability to not lose system memory "state". You turn off the machine, and the contents of memory remain for the next session.
Can you imagine a windows XP "state" that has never been rebooted? How about a continually running process that has a memory leak?
Eventually all machines need to be rebooted (some much less than others). That means re-creating a "clean" system state in memory.
-ted
Yes and it just gets worse as chip densities increases. That's why IBM invented Chipkill (which is essentially RAID-5 for ECC RAM banks). The error rate for 1GB ECC memory-equipped server is 9 outages per 100 servers over 3 years IBM whitepaper, pdf. Non-ECC ram is probably rediculously high!
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