MRAM Inches Towards Prime Time

levin writes "According to an article over at EETimes, magnetoresistive RAM chips are getting a little more practical. Infineon Technologies released info on a new 16M MRAM component on Tuesday and the read and write cycle times of this chip make it 'competitive with established DRAM.' How long before nonvolatile memory becomes the solution to crash-prone software rather than better programming?"

Comments

What?

[bobintetley]

How long before nonvolatile memory becomes the solution to crash-prone software rather than better programming?

What? A crash-prone program is a crash-prone program, regardless of whether it vanishes or not when you turn the power off.

Re:16M?

[bhtooefr]

However, there are 8 to 16 chips on a DIMM. So, multiply by 8 to get 16MB for a single-sided DIMM, or 16 to get 32MB for a double-sided DIMM. Not good, but for a new memory type, it's catching up quick.

Re:Memory errors are RAMPANT--one every 90 minutes

[NigritudeUltramarine]

No, that's wrong. The truth is that errors in dynamic RAM can be introduced on each refresh. As you said yourself, dynamic RAM needs to be refreshed every few milliseconds--read and rewritten. Each time that happens, it's possible for an error to be introduced. If the refresh circuitry reads the value incorrectly, you get an error. If it writes the value incorrectly, you get an error. The longer the RAM sits around, the more refresh cycles, so the greater the chance for errors. If the voltages aren't stable enough, for example, you'll find a "1" bit refreshed with slightly too low of a current so that when the next refresh comes around, it's read as a "0" as it's been discharging over time and falls just below the threshhold to be read as a "1".

As far as errors not being introduced when the memory is "idle," you're thinking of static RAM. Static RAM doesn't need to be refreshed, and thus actually CAN be idle. So it holds a huge advantage here. Without the refresh cycle, there's no place for errors to be introduced except during the actual reads and writes by the processor.

Re:Memory errors are RAMPANT--one every 90 minutes

[afidel]

Yes and it just gets worse as chip densities increases. That's why IBM invented Chipkill (which is essentially RAID-5 for ECC RAM banks). The error rate for 1GB ECC memory-equipped server is 9 outages per 100 servers over 3 years IBM whitepaper, pdf. Non-ECC ram is probably rediculously high!