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Sun Working to Eliminate Circuit Boards
lokedhs writes "Sun Microsystems is coming out with new chips without connectors. According to the article, this will have a lot of advantages: 'Performance, for instance, could greatly escalate because the speed of transferring data among chips and the number of channels for the transfers would increase. Energy consumption could also decline. Just as important, overall costs could fall, because defective chips could be removed like Scrabble tiles.' This technology will also lead to new CPU's without cache: 'The technique could also allow designers to remove the cache--the large pool of memory currently found on the processor--and put it on a separate chip. Caches were integrated onto processors to amplify bandwidth. Adding cache, however, bumps up manufacturing costs, as it greatly increases the number of transistors. With the bandwidth constraint gone, caches could once again be made independent without it having an impact on performance.'"
What they need, instead is VioletTooth (wireless chip-to-chip communcations). That way, they won't have to worry about alignment problems and such!
One thing is for sure. If they can get this to work and if heat production can be cut down, this would make computing equipment and electronics much smaller. The printed circuit board is one of the big things holding us back from much better electronics miniaturization.
Wow, this announcement reminds me of an awesome book I just read: http://www.kuro5hin.org/prime-intellect/mopiidx.ht ml
so basically they want to stack the chips? umm, heat?
It has to be said, I think that if Sun are seriously thinking of producing such chips then it must be a moderately good idea (they're not monkeys after all), so I wouldn't write it off on the basis of heat concerns.
You've probably noticed that people's noses get bigger as they get older. That's because old people are huge liars.
Well, this is offtopic, but there's no place to discuss the problems Slashdot has been experiencing, so why not here? If the admins won't provide an appropriate forum, we have no other choice.
Does anyone have any idea what's going on here? I can't be the only one who wishes for a front-page story explaining why Slashdot is so amazingly unreliable and broken lately--especially for subscribers who are paying $ for this service.
Shouldn't be a problem.. Have you seen the latency on modern Cache implementations? We're already at a BEST case of 2 clock delays with minimal concurrency. We're seeing 8 and even 16 clock cycle delays for L2 / L3 caches. Cache has always been hierarchical.. The lowest latency is always very small.. What this technology provides is effectively extraction of L2 cache with the complete transparenc y of adding L3 cache.. Think 128Meg L3 cache 8Meg L2 cache; something completely impractical for regular general CPU design.. Since you can "upgrade" your cache by replacing a peer-chip, now you can pay-as-you-go.. Spend a thousand dollars a year, upgrading one cache chip at a time.. And we've seen what's happened with the SDRAM market once commodetized. Pretty soon SDRAM may dissapear completely, being replaced by (albeit high power) gigabyte SRAM L4 modules.
If cost effective, and if they can get past the alignment issues, this is spectacular.
-Michael
The thing is cache latency is still for the most part pretty huge. With pipelines as deep as they are, the cache needs to be really huge to prevent stalls that will totally obliterate performance. Now, if you are able to separate the cache physically while not being restricted in the bandwidth between the external cache and processor by a lack of physical pins and the need for arbitration from other chips (the reason why external cache was so terribly slow) by using capacitive connections, well... the game has changed substantially.
A lot of the reason CPUs have become more and more integrated is simply due to the fact that connecting multiple chips together is the simple fact that there are not enough connections available to keep them separate _and_ fast.
--Kevin
I would imagine that at such low voltage levels, induced current would require a damn near perfect level of alignment between the chip and the "socket".
Well, if they invent a very good self-aligning mounting socket, dirt can be dealt with just by being very careful and using one of those air-in-a-can dusters. This technology would be very expensive, initially, so you could even get one of Sun's guys to come out and do it for you.
That's a nice dream and all, but where the hell are you going to put it then?
I'd bet they put it nowhere. L2 and L3 caches are a kludge, and, if they really achieve huge chip-to-chip bandwidth, they just might not need the cache hierarchy. This is reminiscent of old CPUs, where the system RAM ran at an acceptably large fraction of the speed of the CPU, so there was no L2 cache at all.
-- "Makes Little Debbie look like a pile of puke!" - Moe Szyslak
Actually Sun has traditionally stocked R&D even when everything else is tight as McNealy feels the best way to come out of a slump is fighting. On that I'll give him credit ... though alot of other decisions have been flaky lately.
It is more productive to voice thoughtful opinions (reply) than to judge (moderate) others.
This is a very cool idea and it's the kind of thing I expect from Sun. Once it's stated, the solution almost looks obvious. While there's lots of work needed to make the idea practical, I admire the way they took a big noise problem and used it to propagate signal. It's too bad they are run by someone who thinks that they are going to make their money by licensing software instead of selling chips and licenses to very cool and real inventions.
Friends don't help friends install M$ junk.
I wonder if this could lead to new treatments of spinal injuries? Say you could place a chip intervening between a severed spinal cord. Instead of having to physically attach all those millions of nerve endings, you could have the chip do it by proximity, and carry the signals on past the gap.
BTM
That was the turning point of my life--I went from negative zero to positive zero.
Perhaps the chips could interlock like puzzle pieces. This has an additional advantage of increasing the surface area, potentially allowing even more signals.
Heat is really only a by-product of the problem. The main problem is power consumption. If you have a big enough fan you can cool anything (within reason) but who is going to buy a CPU that sucks 1KW (which is the way the power issues are leading).
FYI: The power issue is only going to get worse at smaller geometries.
Roughtly: Power = Switching Power + Leakage Power + Others.
The two we are interested in here is the Switching Power and the Leakage power. Up until now Switching power has been the greedy party, but when geometries shrink down to 90nm and below, leakage power really kicks in.
IBM and AMD have done some nifty stuff with strained silicon and silicon on insolutor to try and reduce the leakage power (and therefore the heat).
So heat really will not be solved by just taking it away faster - because there's a whole lot more of it lurking around the corner, to fix the heat issue, you have to fix the cause not the symptom.
[ Monday is a terrible way to spend one seventh of your life. ]
Ground planes alone would just help capture all that leaked RF energy and unhelpfully put it on your power supply return (which also can pick up outside interference and help screw with your chip sandwhich). Stuff can be done about this but you'd still have to have an off chip board with the right set of filters etc.
Instead of screwball stuff I think it'd be more helpful to simply find ways to drastically reduce the number of pins required. Most of these chips are huge because of the 128 signal wide memory/data busses, N control/configuration pins, big address busses etc. Much of this can be replaced with comparatively fewer high speed links.
What I'd rather see is parallel busses being replaced by very high speed serial links (all patented to hell and back of course), perhaps one link per expected peripheral (memory, adjunct processor, i/o bus, video bus, etc.). One could build a very cheap PCB that could almost be hand assembled. The problem is that each peripheral would also have to be compatible with the link. No one builds DDRs with SERDES links for example...
80% of the boards I've designed have been pratically identical in terms of core functionality, but they've been completely different in implementation because of the differing interfaces.