Sun Working to Eliminate Circuit Boards

lokedhs writes "Sun Microsystems is coming out with new chips without connectors. According to the article, this will have a lot of advantages: 'Performance, for instance, could greatly escalate because the speed of transferring data among chips and the number of channels for the transfers would increase. Energy consumption could also decline. Just as important, overall costs could fall, because defective chips could be removed like Scrabble tiles.' This technology will also lead to new CPU's without cache: 'The technique could also allow designers to remove the cache--the large pool of memory currently found on the processor--and put it on a separate chip. Caches were integrated onto processors to amplify bandwidth. Adding cache, however, bumps up manufacturing costs, as it greatly increases the number of transistors. With the bandwidth constraint gone, caches could once again be made independent without it having an impact on performance.'"

Comments

Re:Oversimplified

[maraist]

Shouldn't be a problem.. Have you seen the latency on modern Cache implementations? We're already at a BEST case of 2 clock delays with minimal concurrency. We're seeing 8 and even 16 clock cycle delays for L2 / L3 caches. Cache has always been hierarchical.. The lowest latency is always very small.. What this technology provides is effectively extraction of L2 cache with the complete transparenc y of adding L3 cache.. Think 128Meg L3 cache 8Meg L2 cache; something completely impractical for regular general CPU design.. Since you can "upgrade" your cache by replacing a peer-chip, now you can pay-as-you-go.. Spend a thousand dollars a year, upgrading one cache chip at a time.. And we've seen what's happened with the SDRAM market once commodetized. Pretty soon SDRAM may dissapear completely, being replaced by (albeit high power) gigabyte SRAM L4 modules.

If cost effective, and if they can get past the alignment issues, this is spectacular.

Re:Heat? Naw. Here's some better problems.

[upsidedown_duck]

I would imagine that at such low voltage levels, induced current would require a damn near perfect level of alignment between the chip and the "socket".

Well, if they invent a very good self-aligning mounting socket, dirt can be dealt with just by being very careful and using one of those air-in-a-can dusters. This technology would be very expensive, initially, so you could even get one of Sun's guys to come out and do it for you.

That's a nice dream and all, but where the hell are you going to put it then?

I'd bet they put it nowhere. L2 and L3 caches are a kludge, and, if they really achieve huge chip-to-chip bandwidth, they just might not need the cache hierarchy. This is reminiscent of old CPUs, where the system RAM ran at an acceptably large fraction of the speed of the CPU, so there was no L2 cache at all.