Itanium Retreats To Multis, Opteron Presses Attack

vincecate writes " Back in 1997 Itanium was presented as a compatible extension of x86, and Intel had dreams of replacing high end x86 by 1999 (about min 16 in link). However, the original 2001 Itanium had the 32-bit performance of a much older Pentium so Itanium is viewed as non-compatible. Now with the rise of what Microsoft is calling the "x64" architecture (AMD64 and EM64T), Itanium has been repositioned to the multiprocessor server market."

However, Opterons are designed for multiprocessing. Each has its own memory and built in hypertransport links to make NUMA multiprocessors. So existing Opterons don't need large expensive caches like Xeon MP, nor any glue chips for up to 8-way multiprocessors. This has started the commoditization of multiprocessors. You can now buy a 4-way Opteron for $6000 or an 8-way for $10,000.

There is an interesting interview with Tyan CEO and his assistant that give some info about future Opteron plans. People are working on 8-way motherboards that will become 16-way when duel-core Opterons come out. They also say that the next Opteron core, the K9, will be able to 'go over 60 processors without adding any external crossbar chips.' Another fun plan mentioned is connecting the hypertransport links using fibers for really large systems."

Comments

x86 code size advantage over Itanium

[vincecate]

It is reported that IPF executable images are typically three times the size of equivalent Alpha executables. I used crosstool to make a gcc cross compiler, and found Itanic (IPF) code to be twice the size of AMD64 code. This is a significant architectural price/performance difference when it comes to either cache size or memory bandwidth, and no doubt part of why Itanics are so expensive.

Re:Xeon and Itanium will share the same bus

[questionlp]

The Itanium already uses a modified GTL/GTL+ bus, the only difference is that it runs at a difference speed than the bus used by the current Xeon DP/MP processors. What will happen though is that Intel will use a common socket, bus and socket for both the Xeon and the Itanium.

Intel and HP are already doing something like that with their dual-core PA-RISC workstation, as it uses the same socket and chipset as the Itanium... the only difference is that the firmware used was designed for the PA-RISC. That right there shows that the workstation could be converted into an Itanium workstation in the future if HP wanted to.

Hypertransport is great for high bandwidth, but because it is a serialized connection, latency increases. Of course, in large servers, you are going to get pretty high latency anyway... the difference is that the Opteron does not have to share a single bus for both memory and I/O like the Xeon and the Itanium. Higher latency was a trade-off AMD had to make, but at least they are separating local memory traffic from I/O traffic for each processor.

Re:x64 vs x86?

[obeythefist]

But if you want to remove the x, you can't be vague about the 86 - you'd need to reference the full 8086-64, although the CPU's we use today are markedly different from 8086, more like 80586-64, but then the 586 was really the pentium(tm) brand, so to be correct and without using an "x", you have to call it the pentium-64, which is really inaccurate because AMD's K8 hammer family is very different to a pentium internally, much more powerful CPU's. So it just isn't going to work.