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Intel Shrinks Transistor Size By 30%
pinkUZI writes "Intel will announce that it has crammed 500 million transistors on to a single memory chip, shrinking them in size by 30%. " The tech details are sadly lacking in the article - but I'm sure those will follow. Indeed, the Yahoo piece gives the details that "...has created a fully functional 70 megabit memory chip with transistor switches measuring just 35 nanometers."
Actually, from the article, the new techniques make for smaller transistors, that use less juice, leak less energy, and work faster. The heat output per-transistor would be much smaller.
Of course, that's not Intels market. Any heat/space saved will be reallocated for new features (extra CPU cores blah blah).
If you want a cool, slow chip, look to VIA or transmeta. If you really want/need a real Intel, look to the Pentium 4 M's.
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Even funnier considering MOS transistors don't have a B,C, or E. Try drain, source, and gate. :)
You're thinking DRAM, with one transister per bit, but slow (plus it needs refreshing every 60msec or so). Static RAM is mucho faster, with 4 to 8 transistors per bit.
Also, your math is in error. 500M transistors for 70 Mbits works out to 7 transistors per bit. I'm guessing the visible portion of the chip will be 64Mbits and 6 transistors/bit, with most the rest of the transistors allocated as spares. When you make a chip that big, you can boost yield by making spare blocks of memory that during manufacturing can be substituted for bad areas on the chip.
--- Often in error; never in doubt!
Well, sorta.
Smaller transistors generally require less power to operate because they can (actually, must) be operated at a lower voltage. Dynamic (swtiching) power varies with the square of the voltage, so dropping the voltage a little makes the power go down a lot.
But that's just switching power.
As gate sizes shrink, previously negligible leakage (static) power increases. A lot. Now it's no longer negligible at the 90nm and 65nm process steps. In fact, it's getting very close to the same order of magnitude as switching power.
That's a problem because you can limit dynamic power by switching more slowly, or not switching certain transistors at all (think mobile CPU speed throttling.) But leakage power is consumed even if the CPU clock isn't ticking. If voltage is applied to the chip, power leaks.
everything in moderation
"Reduced transistor size by 30%" is an odd way to announce moving from a 90nm to a 65nm process.
Just to help avoid any confusion here, this is not some new clever transistor design or something. It's just another incremental step in process size reduction. It happens every few years. And it's not just Intel -- I know IBM and NEC are doing 65nm right now as well. I suspect TSMC and UMC are also, though I'm not sure (I know UMC had problems in 90nm that they're still fighting with . . )
everything in moderation
The 3.6 gig prescott puts out 115 watts
This article puts the 3.2 and 3.4's at about 103 watts.
This article pegs the Athlon 64 at 116 watts.
Yeah, you are engaged in CPU tribalism/fanboyism, whether you realize it or not. Both chips are pretty much equally "hot". One should use a different yardstick to compare the two.
BTW, this article has the Itanium sucking 130 watts, which is probably where the misinformation came from.
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Your post is accurate and informative in general, but there's one nit I must pick:
But as a rule of thumb, the closer you bunch up the transistors, the higher the electrical leakage.
It's not the bunching up (density) of the transistors that increases leakage current (static power consumption,) it's the gate size. Narrower gates are less good at being the perfect insulators they should be. The thinner dielectric allows more leakage current, and can even break completely if the voltage is too high, which is why smaller-geometry processes often allow (or require) lower operating voltages, which helps reduce synamic (switching) power.
Of course, it's the shrinking of the gates (and the rest of the transistors) that allows them to be bumched up more (placed in higher density,) so maybe you meant it that way . . .
everything in moderation
The actual Intel press release claims that:
"Intel's leading strained silicon technology, first implemented in its 90nm process technology, is further enhanced in the 65nm technology. The second generation of Intel strained silicon increases transistor performance by 10 to 15 percent without increasing leakage. Conversely, these transistors can cut leakage by four times at constant performance compared to 90nm transistors. As a result, the transistors on Intel's 65nm process have improved performance without significant increase in leakage (greater electrical current leakage results in greater heat generation)."
Allow me to restate that: They wouldn't be capable of maintaining their charge for long enough to be useful. The DRAM refresh rates can be measures in KHz, as opposed to the CPU which can be measured in GHz. Running at a KHz refresh rate means that they draw orders of magnitude less power than a CPU.
:-/ And yes, SRAM would have been a better example.
Sorry, I was probably unclear on that.
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Uh, that article was pre-release, and was for an AMD64 FX overclocked by about 15%. In fact, that was the power draw at the highest stable speed they could achieve with a -10C cooling system.
According to this, the AMD64 processors have a thermal design of 89W.
According to this the comparable P4 has a thermal design of 115W.
AMD has nothing to gain by recommending to OEMs that they be able to supply less power than the system requires, and to dissipate less heat. I purchased an AMD64 and find that it runs quite cool without any help besides the retail heat sink and fan (nothing special).
FYI - half of the CPUs in my home are Intel-based. I'm hardly biased for the sake of being biased. However, when I went to build my computer I checked the specs and the prices and found that AMD64 was the best bang for the buck. And in the 64-bit world it is essentially uncontested at this point if you care at all about x86-compatibility. (Granted, that will change, and I look forward to whatever Intel comes out with to compete.)
Quoted from your original post:
That's 10MB per (square?) 35 nanometers.
From the post I am replying to:
Why "wrong"? From the Yahoo article:
"The Santa Clara, Calif.-based company said Monday it has created a fully functional 70 megabit memory chip with transistor switches measuring just 35 nanometers -- about 30 percent smaller than those found on today's state-of-the-art chips."
Now according to Google, there's 10,000,000 nanometers to a cm. Our chip is 35 nm in size. 10,000,000 divided by 35 is 285,714. So we now know that we can put 285,714, 35nm chips in a 1cm strip.
OK, here are your errors:
Original post: No, it is not 10 MB per square 35 nm, the transistors have 35 nm gate lengths, simply meaning the lenth of poly cut to form the gate is 35 nm, probably at least 3x as wide (can't really say without detailed knowledge of their layout). The overall transistor foot print is going to be MUCH bigger than a 35 nm square, as you haven't even included the source and drain, let alone contacts!
Now on to your second post. You say "Our chip is 35 nm in size." It is obvious you do not work for Intel if you are saying your chip is 35 nm in size. The chip is going to be MASSIVE compared to 35 nm (see above point) once you put 500,000,000 of them on the chip.
My only mistake appears to be in accepting the parent's figure of ~10 MB.
No, you have many mistakes, primarily seeming to be without a clue of semiconductor processing or circuitry.
Any questions?
Yeah, do you feel like uttering any other ignorance while you are here today? I apologize for being rude, but it seems to me like you are trying to put on an air that you know what you are talking about when it is blatantly obvious you are without a clue.
With all due respect, I think you're confused. For the same operating voltage, dynamic power does not decrease with decreasing gate size/transitor size.
P=1/2*Ceff*V^2*f*N+Q*V*f*N+I1*V
where P is power consumption, Ceff is effective load capacitance, f is frequency, V is source voltage, N is signal switching coefficient, Q is charge due to through-type current, and I1 is leakage current.
While the actual gate capacitance driven may be reduced by virtue of it's smaller size, the effective capacitance (that "seen" by the driver) stays roughly the same, or may even get higher from parasitic capacitance. The only thing sure to change is the leakage current, which will increase as gates shrink.
Maybe this will help you understand.
everything in moderation
The problem is production, not cooling. By making the CPU die bigger, you a) decrease the number of dies you can make on a single wafer, which costs a fixed amount to produce, thus making each CPU more expensive; and b) defects that would have only scrapped 1 die out of 300 will now scrap 1 die out of 50, thus making the yields lower, raising the cost per die, making the CPU more expensive to the consumers. Decreasing the die size and increasing the wafer size leads to cheaper chips which is a Good Thing (tm). A nice side affect is that it also allows for higher clocking, which is both good (more ops per second) and bad (current leakage and heat issues). Smaller dies also consume less voltage, which is again a Good Thing (tm). Just have to get current leakage, a Bad Thing (tm), down and the chips would run cooler and consume less power. This new process is better at current leakage, so thats a Good Thing (tm). All in all, making the CPUs smaller is good for Intel and good for the consumer.
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There are three components to leakage current in DSM CMOS devices. From here in order of magnitude: (1) source-drain junction leakage current (2) gate-direct tunneling leakage, and (3) sub-threshold leakage current.
And while neither of us pointed out all three, the fact remains that it's not the "bunching up" of the transistors that increases leakage, it's the gate and transistor sizes (which tend to scale together.) Which was the point I was trying to make.
If you think gate leakage is negligible compared to sub-threshold leakage, you'd better tell the IEEE and all those people working on high-K gate dielectrics.
everything in moderation