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Intel Shrinks Transistor Size By 30%

Posted by Hemos on from the how-long-until-market dept.

pinkUZI writes "Intel will announce that it has crammed 500 million transistors on to a single memory chip, shrinking them in size by 30%. " The tech details are sadly lacking in the article - but I'm sure those will follow. Indeed, the Yahoo piece gives the details that "...has created a fully functional 70 megabit memory chip with transistor switches measuring just 35 nanometers."

4 of 258 comments (clear)

  1. EE Times article by PIPBoy3000 · · Score: 5, Informative
    There's a better article here

    Within the 65-nm process, Intel has also devised a second-generation strained silicon technology. "The second generation of Intel strained silicon increases transistor performance by 10 to 15 percent without increasing leakage," Intel said. "Conversely, these transistors can cut leakage by four times at constant performance compared to 90-nm transistors."
  2. Re:70 Megabit? -- Static RAM, not DRAM. Also 7T by elwinc · · Score: 5, Informative

    You're thinking DRAM, with one transister per bit, but slow (plus it needs refreshing every 60msec or so). Static RAM is mucho faster, with 4 to 8 transistors per bit.
    Also, your math is in error. 500M transistors for 70 Mbits works out to 7 transistors per bit. I'm guessing the visible portion of the chip will be 64Mbits and 6 transistors/bit, with most the rest of the transistors allocated as spares. When you make a chip that big, you can boost yield by making spare blocks of memory that during manufacturing can be substituted for bad areas on the chip.

    --
    --- Often in error; never in doubt!
  3. Re:In related news... by randyest · · Score: 5, Informative

    Your post is accurate and informative in general, but there's one nit I must pick:

    But as a rule of thumb, the closer you bunch up the transistors, the higher the electrical leakage.

    It's not the bunching up (density) of the transistors that increases leakage current (static power consumption,) it's the gate size. Narrower gates are less good at being the perfect insulators they should be. The thinner dielectric allows more leakage current, and can even break completely if the voltage is too high, which is why smaller-geometry processes often allow (or require) lower operating voltages, which helps reduce synamic (switching) power.

    Of course, it's the shrinking of the gates (and the rest of the transistors) that allows them to be bumched up more (placed in higher density,) so maybe you meant it that way . . .

    --
    everything in moderation
  4. Re:In related news... by randyest · · Score: 5, Informative

    There are three components to leakage current in DSM CMOS devices. From here in order of magnitude: (1) source-drain junction leakage current (2) gate-direct tunneling leakage, and (3) sub-threshold leakage current.

    And while neither of us pointed out all three, the fact remains that it's not the "bunching up" of the transistors that increases leakage, it's the gate and transistor sizes (which tend to scale together.) Which was the point I was trying to make.

    If you think gate leakage is negligible compared to sub-threshold leakage, you'd better tell the IEEE and all those people working on high-K gate dielectrics.

    --
    everything in moderation