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Analyst Doubts Intel's Dual-Core Demo
bakeacake writes "At Xbitlabs they have a article on the possibility that Intel's Dual core Preview at the IDF was not real. Would Intel sink this low?
"An analyst expressed doubts about demonstration of a 'real' dual-core microprocessor during an Intel's recent demonstration at Intel Developer Forum Fall 2004 in San Francisco, California. Insight's Nathan Brookwood believes that Intel was most likely to showcase a dual-processor system instead of a dual-core processor-based system during the show.""
It is two processors on a single die. It would be like having a dual processor system, but only needing a single socket to support it. Now add in Hyperthreading and it would appear to be a 4-way system. Many people are really excited about this, and it is definately a cool engineering feat.
Just a single CPU die with two CPUs on it. If the board can support it, it's like plugging two CPUs into one socket.
This is quite easy for AMD because of how bus logic works. The Athlon 64 series use an integrated memory controller, and normally, a second CPU uses the same connection to the system RAM that the first one does. (ie, one Hypertransport connection is shared, by design, between two CPUs.) So a dual-core CPU is trivially easy for them to implement, relatively speaking: they have space and heat issues, but all the architectural design work is done already.
Intel, on the other hand, hasn't designed this way. Instead, for years now, they have been totally focused around more and more clock speed. This has left AMD scrambling, becaus their chip designs get more work done per clock tick, so a 1600mhz AthlonXP will keep up quite nicely with a much higher-clocked P4. But consumers, thanks to Intel mostly, don't understand that, and so AMD came up with their numbering system instead. (they were lucky this worked, because at least one prior attempts at this, by Cyrix, failed utterly.)
Well, the worm is turning. Intel's aproach, that of "more megahertz, dammit!" is very rapidly running out of steam. They have been selling people for years on megahertz, and suddenly they're in the position where they can't increase megahertz easily anymore. This is a BIG deal for them; all those billions spent 'educating' consumers on something that wasn't true is coming back to bite them.
A dual-core Prescott will not be an easy thing, and will require substantial motherboard and chipset changes. And they have a fundamental bandwidth problem; P4s need very high memory bandwidth to really get good. The P4 didn't truly hit its stride until it went to a quad-pumped 200mhz bus... 800mhz effective RAM speed. At that point, the P4 architecture finally sits up and really starts singing. But doing a dual-core chip means that both CPUs have to share bandwidth, so to maintain performance, they'll have to go to a 1600mhz bus. That's not likely in the near future.
AMD is doing the exact same thing, but the A64 design is much less clockspeed- and bandwidth-intensive. It gets more work done per clock tick, doesn't hit the RAM as hard, and runs cooler. So it's a natural for dual-core. Forcing the P4 into that same mold, on the other hand, is a move of desperation by Intel. It won't work very well, but their crank-the-megahertz strategy suddenly isn't working AT ALL.
From what I can see, Intel is in trouble.
Uh, actually there are significant advantages to having a shared cache depending on the application. While it may not be too obvious, and its not true in all cases (ie 2 single core processors with 1MB L2 cache each will be a dual core with 1MB L2 in most all situations). In general however they will give the dual core chip a larger L2 cache to make up for the fight between the two processors to use (often including heuristics to ensure that one processor doesn't kick out all the other processors data from cache).
Where then do performance gains over simple dual core operation come from then? Well in many multithreaded applications there is a significant ammount of shared data. When processing this shared data only one copy needs to exist in the L2 cache. On top of that if one core is using the data (or used it recently) and the second processor needs to use it, the data exists in the first processors L1 cache (generally dual cores won't share L1 cache due to the necessity to locate L1 cache near the core of the processor for speed reasons. When this happens the 2nd processor must wait longer then normal for the first processor to update the L2 cache (cache coherence protocols and the fact that L1 cache is duplicated in L2 cache), but this is still an order of magnitude faster then a standard dual processor setup.
So there you have it, the advantages of a shared cache.
Phil