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IBM Claims World's Smallest SRAM Memory Cell
nokiator writes "IBM issued a press release today claiming that it has built an SRAM memory cell that is ten times smaller than those currently available.
My interpretation of the PRese in this release is that IBM will be able to build 256Mb or 512Mb SRAM chips or integrate 32MB or more SRAM into processor dies for cache applications in the future. Of course, showing some SRAM cell prototypes is a long ways from being able to manufacture this technology in a cost effective way.
There is no information in this PR about the speed or power consumption of SRAM blocks that can be built with this new cell technology. This is not likely to be a potential DRAM replacement for mainstream applications as DRAM already offers more than ten times density compared to SRAM at much better cost."
The memory modules you put in your computer are composed of DRAM chips. DRAM uses a capacitor and a transistor per cell (plus sense amps, decoders, etc.). DRAM requires refresh (the charge on the cap leaks off) but is relatively low-power and very dense. SRAM uses no capacitors, but more transistors (4 or 6) per bit; it's higher-power but faster and doesn't require refresh.
So, SRAM density has nothing to do with DIMMs you put in a computer. It's used for on-chip caches (and off-chip caches), but is too expensive for main memory. Denser SRAM means that Opteron you've got with 1M L2 cache could have 4M or 8M if IBM can mass-produce the stuff.
DIMMs usually have 16 chips (18 for ECC modules). So, if you have 512Mbit DRAMs, you put 16 of them on a module and you get 8Gbit = 1Gbyte. Gigabit DRAMs can make 2GB DIMMs. 2Gbit DRAMs are needed to make 4GB DIMMs; they cost hundreds of dollars each (and you need 16!), which is why 4GB DIMMs are so amazingly expensive.
High-speed Road Trip (18.000KPH)
Their server division buys most if not all of its parts from other companies, excepting perhaps the PPC chips. Cases, CPUs, memory, video chips, and most likely even motherboards are manufactured by other companies, who probably also have a more direct hand in design than does IBM, which may only do oversight engineering such as reviewing final designs to ensure there are no significant bottlenecks or thermal build points.
You can never go home again... but I guess you can shop there.
Bullshit... I once saw a low end intel IBM server... yeah... IBM is just like any other incorporated beige box assembler... Dell? Oh, you're so much wrong... listen: redundant monster fan, redundant power supply & cabling, redundant motherboard chipset, HotSwap PCI cards, HotSwap and (configurable) Redundant RAM (have you ever heard of RAM RAID? is that Redundant Array of Expensive Ram?)! You can pop the Bleedin' memory sticks from the machine Live! (I mean, the Dimm socket braces have leds identifying the faulty stick!)... drums roll... HOTSWAPPABLE BLOODY CPU BASKET (two at the same time... the thing waits brainless for the tech to drop the new one)! Yeah... just like that Dell... I'm daed shure this beast doesn't even let Winders touch the metal, there must be some virtualizing layer because I can't possibly believe Windows could ever survive in such an advanced machine without self-formatting in shame! Now boy, go blow your nose and play with your cold-cathode modded water-hyped P4EE...
Mi domando chi à il mandante di tutte le cazzate che faccio - Altan
Actually, it used to be based solely on the width of the general purpose registers in the CPU, implying that the CPU could process data in those sizes with one ALU operation (the ALU was as wide as the general purpose registers).
The 68000 you mention was considered a 32-bit CPU, or at least a 32/16 (32-bit internally, 16-bit data bus) as was the 68010 and it wasn't until the 68020 when it had a 32-bit data bus as well. There was even a variant that was the 68008 that was identically equivalent to the 68000 except it had an 8-bit external data bus. I have occassionally seen the 68000 referred to as a 16-bit processor, but the vast majority of times I've seen it discussed call it a 32-bit CPU.
As far as I remember, no processor has ever been 'named' relative to the address bus width. Even in the PC world I can't remember any time when the CPUs were 'named' relative to the address bus. Many 32-bit CPUs didn't have the full 32-bit address bus externally accessible. I can't think of any 64-bit CPU that has the full 64-bit address bus externally accessible.
As far as cache storage of data, the data formats are independent of the pointer size. The blanket statement that a 64-bit CPU effectivly 'halves the cache' is not true. If you have a program that deals only with pointers, then you'd have a point but 'int' on a 64-bit CPU is the same as 'int' on a 32-bit CPU (both being 4 bytes or 32-bits). It *is* true that a program compiled for 64-bit ISA will use *some* more cache, but that is entirely dependent upon the program itself. Again, a program that uses pointers a lot may use more cache than the same code on a 32-bit architecture, but a program that uses few pointers may not use much more (if any more) than the 32-bit counterpart, depending upon the datatypes used.