World's Thinnest Flash Memory Cell Unveiled

qorkfiend writes "Measuring a scant 20 nanometers across, Infineon AG's new nonvolatile flash memory cell could lead to 32 gigabit flash chips within the next few years. The cell contains a unique structure with a fin for the transistor to avoid nano-scale physical effects and uses 90% less electrons than today's memory to store data."

Comments

Real Solid State Computing

[Jozer99]

Wow, now there might be a practical inexpensive method for solid state servers.

iPod

[sh1ftay]

Cool, just in time for a flash based ipod.

Increased susceptibility to quantum effects?

[EQ]

90% fewer electrons? Does this mean less resiliency/redundancy in the chip - how vulnerable is this to quantum effects - or simple radiation?

Re:Increased susceptibility to quantum effects?

[m50d]

It makes it more vulnerable to radiation, but ram is already checksummed for that. Wouldn't want to use it in space though.

does this mean

[museumpeace]

90% less current and since power is
I-squared R
that REALLY cuts the power dissapation which his the brick wall most silicon vendors now approach?

Re:replacement?

[databoing]

Well, see, the problem with that is that Flash Memory is great for reads, but writes tend to wear out the chip. Writes require a higher voltage to perform (1.5V compared to 0.2V, I think. That may be wrong, use google) and so use as a replacement HD tends to shorten the lifespan of the device to a few months.

Using a flash memory device as a storeage place for things unlikely to change frequently (bootable linux for troubleshooting, encryption keys, etc) doesn't do much for the wear-and-tear of the memory, though.

90% less = 81% lesspower too?

[Transcendent]

Since there is 90% less electrons to move, then there would be 90% less current. Power is I^2R, so (.9I)^2R = 0.81P

Sounds very good for portable devices, although I doubt the power consumption of flash cards was that significant (compared to an LCD with a backlite).

Although, my pen drive does get pretty warm when I'm doing enough reading/writing to it, so maybe there will be a significant benefit.

The real point

[eadint]

While everyone is complaining about math issues and how gbit and gbyte relate i think the real point is RW speed, current flash chips have horrible RW speeds my 1 GB flash card takes almost 1/2 hor to download. so it would take 16 hours to get my data (photos) of a 32 Gbyt card that would make it compleatly impractical. i would prefere to see a card that has at least CDROM read transfer speeds. that would be something worth buying.

90% Fewer Electrons!

[0x0000]

Now there's a marketting phrase! Can we expect IC manufacturers to start publishing an "electron count" for their products? How many ways can that be spun into deceptive marketing .... "Well, Brand X claims they're using fewer electrons than we are, but they're not telling you about the anicillary effects that consume 27% more electrons than the Acme Electron Lite Reduced Electron Count (REC) model. The fact is, our revolutionary REC technology represents a quantum leap in facilitated innovation..."

smaller, faster, sooner

[Doc Ruby]

20nm across means 1cm^2 can hold 250B(illion) cells, each 1 bit. That's 32GB(yte) chips in a cm^2. I have a 1GB SD chip in my Treo's SDIO slot, which cost $67 today. A 32GB chip is only 5.7 times denser (in each planar dimension). In the other direction, a 32GB SD chip (similarly less dense in the same 32/5.7x scale) today costs $10, which includes the overhead of the rest of the package.

I'm not so jaded that I think 20nm isn't so small. These numbers really scream how tiny a scale in which we're already producing engineering commodities. I just think that we'll see an increase in Flash density, driven more by the exploding market and R&D money than by physical and engineering limits. 3D memory array packages are long overdue: how about taking that 1GB chip, and arraying its 200nm cells within a 32Kx32Kx0.5K array, a millimeter-thick sandwich of cells and address bus layers, for a 0.5TB chip? 4 of those in an SD package would make a great 2TB cell the size of a quarter-dollar coin. By the time the packaging is engineered, the tech discussed in this thread will have shrunk cell size by at worst half, so 8x0.5TB layered chips can not only offer 4TB, but the address busses can offer a hypercube (or higher-order) topology, for parallel accesses.

Then we can get really fancy. Dedicate 1% of the Flash cells among the busses to FPGA logic cells in 100-cell clusters. That tiny parallel machine is now potentially the fastest supercomputer on the planet. That path to a "hypernanocomputer" is purely evolutionary, in terms of IC fabrication. If that were say, Intel, IBM or Fujitsu's roadmap, we could be there within 5 years, maybe 2-3 years. C'mon, someone over at Infineon get to work and really impress us.