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High School Dropout, Self-Taught Chip Designer
circletimessquare writes "The QVC television shopping network has recently found a hit in its product the C64, which emulates the classic Commodore 64 in a small form factor, a joystick. But the story of the designer of the product is more interesting than the product. Meet Jeri Ellsworth [NYTimes. You know what that means], whose life story emulates the golden age of garage-based computer design. She is proof that the passion of the homebrew electronic hobbyist is still a viable force in an age when well-funded and well-staffed corporate design teams dominate chip design."
The soul-saver strikes again (Karma Free, for your pleasure):
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Maybe Bill Gates should have stayed in school and got a degree. He could have been rich, I tell you!
You do realize that Bill was rich before he founded Microsoft, right? His father is a millionaire.
You haven't worked much with FPGAs, have you?
FPGAs are programmed in Verilog or VHDL; it's not much different from programming a computer. All you need is a development board with the FPGA plugged in (the FPGA makers make eval boards specifically to support this), and a connection to your PC so you can download the compiled design into the FPGA.
The problem with FPGAs is that they're very similar to SRAM, and when they lose power, they lose their programming. So they have to program themselves every time they power on, meaning you need a separate ROM chip on the board for it. Worse, because of this and because of the sheer cost per chip of FPGAs, they aren't very good for designs with large production volumes (they are good for small volumes, though, because you don't have to get a custom chip made, which has a high initial cost). So, all you have to do is get your FPGA design converted to an ASIC; there's several companies that specialize in exactly this.
Basically, all this girl had to do was do the actual HDL design at home, test and debug it on a prototype board, then when it was finished send it to a manufacturer to have them make ASICs in large volume from it. You don't need your own fabrication plant any more than you need your own photo developing lab to make photos.
L-edit is a polygon pusher. You are going to be pretty damn persistent to do anything more than a puny digital design in that.
For real digital layout you want to use Astro/Synopsys, Encounter/Cadence, Blast Fusion/Magma or Pinnacle/Sierra (Just maybe). None of these are going to cost you less than a few $100K.
Of cource before you to the point of doing layout you likely want to do synthesis (Although it is not beyond human capability to hand generate netlists). Design Compiler/Synopsys is pretty much the defacto standard but both cadence and magma has credible alternatives.
After layout you want to check your design for timing. To do this you want a Static Timing Analysis tool (Primetime from Synopsys is pretty much the only choice here for sign-off quality, though you might live with what your back-end tool has built in if you feel brave). To feed the STA tool with good data you need to extract the circuit: StarXTRC/Synopsys, Fire & Ice/Cadence, CalibreXRC are the prime contenders.
In addition you might want/need to do:
- Formal verification (To verify your final netlist conforms to your design)
- Rail analysis (To verify your power grid is adequate)
- Thermal analysis (To check your device won't melt of fail due to too high junction temperature)
- Crosstalk analysis (Check for parasitic effects on timing. Required for designs on 0.13um and better)
A complete tools suite for digital design will likely set you back $1000K. Naturally a lot of smaller designhouses will outsource the the implementation, but they will at minimum require simulators (minimum $5000 a seat) and synthesis ($100000 pr. license)
As for fabbing, $500? That would be a mighty sweet deal, even for a shared MPW run. With academic discounts and on an old process you might be able to get a slot on an MPW for $5000. On a reasonably modern process (like 0.18um) a engineering run with 6 prototyping wafers (i.e. not a MPW) will set you back somwhere between $50K to $200K
> 1) Implement a 6502 processor. There is a free core or two floating around, which she likely used. Still not exactly trivial, though.
No, she did her own core, which is both smaller and faster than the free cores out there.
> 2) Reverse-engineer and implement the DRAM circuitry. The design does not use DRAM, but you still need to emulate certain portions of the hardware for timing reasons. When DRAM refreshes, the processor has to snooze.
The NTSC unit is SRAM based. The C64 uses transparent DRAM refresh during the VIC's half of every cycle. The PAL unit will use SDRAM.
> 3) Reverse-engineer and implement the SID sound chip. Fairly major headache.
MAJOR headache.
> 4) Reverse-engineer and implement the video circuitry. Major headache. This system even had hardware sprites.
Yes, it took her years, and there are still timing glitches. It's amazingly compatible though.
5) Reverse-engineer and implement the different hardware ports.
I believe this was fairly easy though.
> 6) Include a bridge that would allow a PC keyboard to emulate a C64 keyboard.
IIrc that's a small state machine and a matrix, nothing too hairy.
> 7) Emulate a cassette drive and load it with warez.
That was done in software by Adrian Gonzalez. The NY Times article concentrated on Jeri herself, so I guess it's forgivable that they didn't mention that there was a software team as well (Adrian and Robin Harbron were the main programmers, plus me and Mark Seelye helped patch games).
> 8) Implement the analog bits of the video and sound circuitry. Maybe somebody else did this.
Nope, all Jeri.
Those people doubting her hardware skills really shouldn't talk without checking facts, and if you think that designing things in VHDL is as simple as programming in C you need a clue. No, make that two. And for the record, it's designed with a mix of VHDL and schematic capture.
READY.
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