Intel's New Chips, High Power And Low

sebFlyte writes "Centrino has been one of Intel's major successes of late, and they've just released the replacement, Sonoma. ZDNet has stripped the new chipset, and published a review of the new kit with all the technical details of what this new chipset will do for your laptop." ZeroOne42 adds a link to Hardware Zone's exhaustive look at Sonoma, "complete with benchmark results between a Sonoma notebook (Fujitsu E8020) and a Centrino one (Gigabyte N512). Looks like Sonoma is closing up the technological gap between desktops and notebooks." And on the desktop side, foxalopex writes "It seems that Intel's new dual-core CPU chips will have some of the highest wattage ratings ever seen on the X86 CPU market, which, according to Tom, wasn't what they initially said would happen. I guess this isn't too surprising seeing how AMD's been beating them on power usage in the last several revisions of chips."

Comments

All the rush... why don't they get it right?

[atcurtis]

I think that they may be taking the wrong approach by putting 2 whole processor cores on the same die...

We have SMT (HyperThreading in Intelese) which in my opinion is a pretty decent idea... just a crying shame about how they set about doing it. They sacrificed the silicon used by the original P4's integrated RamBus memory controller and put in the necessary silicon for their HT technology. The idea of getting an extra CPU for 'free' in the current HT processors doesn't work because in a demanding application, most of the execution units will be busy anyways.

Because of this, many old RamBus P4 machines can outperform their newer P4 siblings - mostly because the newer P4 do not have an integrated memory controller and have to go through the IO originally for peripherals. (ok, they are fixing this with the much higher pincount chips than the 1st gen P4 which did not need all that IO due to integrated RDRAM controller)

Instead, I believe that they need to design a processor with the original intent to be hyperthreaded (instead of the P4's original intent, to use RDRAM). What this means, is perhaps provide many execution units, maybe 50% more than what a single processor requires, and then make it look like 2 CPUs. Or perhaps double or triple the number of units and make it look like 4 CPUs to the software.

So... What they need for the consumer is a high-pincount device which is truely designed for hyperthreading (ie, has enough execution units available to be able to perform nearly as good as having a whole 2nd CPU)
And for the server market, bring back the integrated RamBus controller, still have plenty of pins so that the server can have perhaps 4 or more RDRAM channels to keep the data flowing fast enough to keep the 4 SMT logical processors occupied. (IIRC, the original P4 has 2 RDRAM 800 channels)

And while I am in my Intel rant mood, I'll criticise the Itanic... Surely with the EPIC architecture, all that branch-prediction and other crud they have in the processor is unnecessary... They need to cut away 2/3rds of the silicon, and get people to write compilers which really do work for them. IIRC, the whole point of all that extra cruft is to make it perform ok for brain-dead compilers. Either they get decent compilers out there (perhaps, open-source their Itanic compiler optimiser) or admit that EPIC was "another nice idea, pity it doesn't work in practice".

Rant off.

I still prefer Intel x86 CPUs to AMD's... but mostly because of a kind of weird loyalty to a chip manufacturer whose CPUs have been in my PCs since my old IBM PC/XT...