Slashdot Mirror
Dual Core Intel Processors Sooner Than Expected
Hack Jandy writes "AnandTech reports that Intel's Smithfield processors are going to get here sooner than they originally predicted; most likely within the next few months. Apparently, the Intel roadmaps reveal that the launch dates for next generation desktop chipsets, 2MB L2 Prescotts and Dual Core Smithfield processors (operating at 3.2GHz per core) are almost upon us - way ahead of the original Q4'05 roadmap estimates. Hopefully, that means Intel will actually start shipping the new technology instead of waiting four months after the announcement for retail products."
This means I can shut my furnace off this winter, instead of waiting until the end of 05.
You see? You see? Your stupid minds! Stupid! Stupid!
Has anyone stopped to look at modern software while thinking about Dual-Core?
Both Intel and AMD have decided upon dual-core as the future of desktop computing. There will be no more massive Mhz increases... instead the focus is now on parallel computing.... But, seriously, how many CPU intensive applications outside of the server arena take advantage of SMP?
As someone who has ran dual-cpu workstations for years, I can personally attest to the fact that 99% of CPU heavy tasks do not make use of SMP.
Think about it... That copy of Doom3 or Half-Life 2 that you just bought, that runs like shit on even top-of-the-line hardware, isn't going to run any better on Dual-Core, because these games are not designed to run multiple threads simultaneously. Neither do most archival programs (WinAce, WinRar, WinZip, SevenZip, etc etc). Nor do many of your encoding tools (though FlaskMPEG and GoGo-No-Coda are noteworthy exceptions).
As a geek, I can attest that the *nix arena isn't much better. Just because the source is open and available does NOT mean that the author(s) ever considered coding CPU intensive tasks for multiple processors. And "porting" tasks from single threaded to multiple threads is NOT a simple task. This is one of the reasons that there are Computer Science degrees -- writing good SMP code isn't something you learn at technical schools (or even half the full Universities out there).
Don't get me wrong... as someone who has ran SMP boxes for the past 10 years, I'm really excited about Dual-Core. But don't expect it to be worth a whole lot for the immediate future... as no one outside the server arena really codes for SMP.
/dev/random
http://www.hugeurl.com/?ZTlkODQ4ZWE5MzM2Y2E2ZjhlN
Today's CPUs are, in the final analysis, little different than the 386 launched in 1985. Notable exceptions are in details like feature size and operating frequency. Other significant differences are in the pipelining logic, crufted on instruction sets (mmx anyone?) that are rarely called into action, cache and pinouts.
.09 micron process... consider that the 386 had 275,000 transistors- compared to the P4s 42 million. You could fit around 150 386s in the space (on the die) of a single P4.
Now, take a step back and imagine what a classic 386 would look like on a
Now, of course there are many advances to consider over the 386, but fundamentally, that processor logic is capable of handling 99% of 32 bit computing tasks. They may have done so slowly, but there you are.
My thinking is, they could use some of this old logic, buff it up a little to accomodate some modern techniques and carve it all into a single die. Imagine a CPU with 64 simple processors, 4Mb of cache and some controlling logic running at 3-5 Ghz. All this in the space of and at the (manufacturing) cost of a single P4.
This chip could be used in clusters like nobody's business. An array of 128 of these processors could simultaneously handle 8,192 active threads.
What use would it be? Off the top of my head, this would be perfect for real-time monitoring, transaction processing, switching and so forth. There would also be serious advantages in the desktop space as compilers and kernels were built to adapt to the new distribution of resources. Image processing could be handled using the same techniques as SLI cards use to split the tasks up over two or more video cards, and any other large body of data could be simlarly broken up. Compilers would be designed to break a program up not into a paltry 2 or 3 threads, but into dozens. Speed and responsiveness would skyrocket, while fab costs and board speeds remained stable.
This might be the logical outcome of the current drift towards multiple CPUs per die, and it could also unite and surpass the schools of CISC vs RISC, as strategies from both would benefit the endeavor.