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Pentium 4 6XX Sequence and New EE P4s Launched
Mojo-Dog writes "Today Intel took the wraps off their new
Pentium 4 Processors with EM64T extensions for 64-bit computing. The
Pentium 4 6XX Sequence and Pentium 4 3.73GHz are based on Prescott 2M cores with
a full 2MB of on-chip L2 cache as well.
HotHardware.com has a full review with benchmarks posted of these new P4s,
many of which also offer Intel's SpeedStep technology for power savings and
improved thermals, which has been available in Pentium Mobile CPUs for some time
now."
"older" P4 will have a price drop,which will be good for People saving 50$ on a new System.
... of this new CPU is how little power it uses compared to older Prescotts:
. htm
- 600/index.x?pg=16
http://www.hardcoreware.net/reviews/review-263-11
http://www.techreport.com/reviews/2005q1/pentium4
Load temperatures are the same levels as idle temps on the old prescotts!
Item 2 isn't a "design error", it's a trade-off at any moment in time whether you support 64-bit addressing, doing so means a lot more transistors, and if (as with Intel) most of your customers are buying mid-range desktop machines that's a bad trade in 1992, in fact it was still a bad trade as recently as 5 years ago.
Item 3 is an improvement, but you mis-described NX, it doesn't "prevent buffer overflows" at all. It's a _marginal_ defense again deliberate stack smash attacks in which executable code is written during a buffer overflow. Buffer overflows have been used by Black Hats quite happily on Alpha, MIPS etc all these years despite non-executable stacks. It remains to be seen whether the development cost for this feature pays for itself in terms of raising the bar for black hats.
Item 1 is a trade-off again, but one that Intel should have made years ago, perhaps when they designed the 386. 128 registers means a lot more silicon, yet many inner loops will never use more than a dozen or so registers, meaning you either make price/performance worse, or you sacrifice something else (maybe vector instructions) to keep costs down. Every designer makes their own decisions here, and they're validated in the market. Eight wasn't enough, Sixteen is definitely closer to the sweet spot.
AMD made good trade offs with x86-64, they were rewarded in the marketplace and Intel are jumping on the same bandwagon now with EM64T.
RISC processors always have more cache than CISC processors, it's part of the design tradeoff. RISC takes less silicon to implement the core than CISC, which leaves more room to dedicate to the cache. Also the same complex operation requires more instructions on a RISC than a CISC, thus you need more L2 to keep the same amount of functional code in cache.
11*43+456^2