Toshiba Demonstrates Cell Microprocessor

Cybro writes "Toshiba has demonstrated some cool applications for the Cell Microprocessor. They also revealed that they have written their own OS for the new processor. However the article on TechOn does not reveal the license of the OS."

Comments

I am still

[Anonymous Coward]

totally baffled how one could write something for the cell that we would traditionally call an "OS". At least, a time sharing OS. Who gets to use the SPE/APU/SPUs, and when? The attatched memory on the SPEs is nontrivial to swap to memory, and it seems absurd to think that it would just be done offhand with a context switch. Yet, context switches must happen. So are SPEs merely given to processes, who get to keep them, so that the main processor is switching betwen processes normally in a preemptive style but the SPEs stay under the control of single processes?

Or is the Cell OS Toshiba's using here non-multitasking or cooperative multitasking? Or what?

Re:I am still

[adam31]

I am also baffled. But the SPE has a memory size of only 256kb and 25 GByte/s bandwidth to main memory, so it's not like a context switch is out of the question. Also I'm pretty sure that each SPE can run 2 threads SMP (or is that just the Power chip?)

It probably is a combination of the method you describe (where a SPE is dedicated to a thread) and traditional pre-emptive... And it probably boils down to the more processor-intensive threads get their own SPE, while a couple SPEs are dedicated to context-switching threads.

To me, that part is not as baffling as how programs are going to be written in the first place. A thread will have to communicate all the memory accesses it will need to make to prefetch all that data. On the PS2, we use environments like this, where that memory would be double- or triple-buffered so we can simultaneously stream, process, and write-back... but that's hand-written individually for the hardest-core processing pieces, where memory accesses are predictable and sequential. How to do this in a general way to make the process easier on application developers?

That's never really been a concern for Sony...

The interesting thing to me here

[Anonymous Coward]

Isn't even *exactly* how impressive a multitasking feat it was, but that if I'm reading the article right, the 48-stream decoding thing was done *entirely by the auxillary processor units*. That is, the "SPE"s. The main [PPE] processor in the Cell was apparently not really doing anything at the time. This seems to bode wel for the usability of the SPEs.

The Perfect OS for the Cell Processor

[MOBE2001]

I got the perfect OS for the Cell Processor. I just need funding. :-D

The COSA Operatin System

See also the link below.

Probably not an "OS" in the common sense

[Lemming Mark]

[ disclaimer: this is speculation but it's informed speculation - hopefully useful ]

It's worth bearing in mind this is unlikely to be an OS in the common sense. I'd rate it very unlikely that this OS supports such niceties as filesystems, network IO stacks, protected processes, etc - or that it ever will.

Rather, it's likely to be a shim (albeit a clever one) for insulating the developers of embedded-style applications from the real hardware. I wouldn't be surprised if this Toshiba OS is actually a "library operating system" which is linked into the application itself.

Don't think of it as an OS in the Linux sense, more as a toolkit / library for Cell programmers. Exactly how a "conventional" OS will run on the Cell is not clear to me but it seems certain that it can support a Linux-style OS well - otherwise it'd scupper Cell's World Domination plans ;-)

Re:perhaps more interesting

[birge]

Agreed. I found that the better article, as well. Especially interesting was this bit:

Q: Cell has 8 embedded "SPE" CPU cores. What is the basis for this number?

A: Because it's a power of two, that's all there is to it. It's an aesthetic. In the world of computers, the power of two is the fundamental principle - there's no other way. Actually, in the course of development, there's this one occasion when we had an all-night, intense discussion in a U.S. hotel. The IBM team proposed to make it six. But my answer was simple - "the power of two." As a result of insisting on this aesthetic, the chip size ended up being 221mm2, which actually was not desirable for manufacturing.

Additional reading: Info on transputers

[Morgaine]

You write: Transputer != microprocessor

You really shouldn't comment on things you don't know anything about.

Here is some info on the transputer family, and links to data sheets on devices in each of the four main families. The T212, T414, and T805 became the most popular. And yes, they're all microprocessors, ie. a little integrated circuit CPU which you plug into a motherboard just like you do a Pentium, and with all the normal features of a normal microprocessor plus a few others of their own, like the 4 on-chip comms links. I've got a couple of T414's upstairs sitting on the shelf.

http://homepage.ntlworld.com/kryten_droid/inmos/im s_transputers.htm -- An intro to transputers

http://www.classiccmp.org/transputer/documentation /inmos/2186.pdf - 16-bit IMS T225 transputer (T200 famiily)

http://homepage.ntlworld.com/kryten_droid/inmos/im s_t414.htm - 32-bit IMS T414 transputer (T400 family)

http://www.classiccmp.org/transputer/t805.htm - 32-bit IMS T805 f/p transputer (T800 family)

http://www.classiccmp.org/transputer/documentation /inmos/4260.pdf 32-bit IMS T9000 virtual-channel transputer

These Inmos microprocessors were right down the middle of where Kutaragi wants to take the Cell, with lots of interdevice communications being handled directly by the hardware. Inmos even made graphics output chips which were often driven by multiple transputers in parallel, so graphics demos were really common on the transputer scene.

Interestingly, after being passed around between various European parties once Inmos ran out of money, the rights to the transputer were eventually sold off to some Japanese megacorp, iirc.