Slashdot Mirror
Self-wiring Supercomputer
redcone writes "New Scientist is reporting on an experimental supercomputer made from Field Programmable Gate Arrays (FPGA) that can reconfigure itself to tackle different software problems. It is being built by researchers in Scotland. The Edinburgh system will be up to 100 times more energy efficient than a conventional supercomputer of equivalent computing power. The 64-node FPGA machine will also need only as much space as four conventional PCs, while a normal 1 teraflop supercomputer would fill a room. Disclaimer: At this point in time, the software needed to run it, which is the key to the project, is vaporware. "
great list of resources from WP on FPGA if anyone's interested in reading more:
You are correct that this is not a new idea; however, I think the original idea for this type of machine was developed in 1936 by Alan Turing.
"Teleporting Rodents with D-Cell Battery Displacement" theory -- IgnoramusMaximus (692000)
"No one has ever tried to build a big supercomputer with these chips before," Parsons says.
That is wrong star bridge systems
http://www.starbridgesystems.com/
have been selling the hypercomputer for some years now.
So, this is still vapourware.
LARC, at NASA, built an FPGA supercomputer. Here's a link to a related paper from 2002. Note, its a PDF.
Additionally, Cray builds an FPGA using supecomputer in its XD-1. It's definitely a nonvapourware project since they've sold over 15 of them. Yes, yes, it also uses Opterons, but they're paired with FPGAs.
Additionally, prior to Seymour Cray's death at the hands of a drunk driver, he was looking into FPGAs as his next stab at supercomputing.
Do you know why the road less traveled by is littered with the bones of the unwary?
There's a company that has been selling this type of system for a couple of years.
They also have their own language called Viva to be able to program the computer.
Link: http://www.starbridgesystems.com/
--- Reality doesn't care about your opinions, it happens anyway and if you are in the way you'll get squished.
I dont know what kind of design you are referring to but synthesizing and doing routing and placement of a circut takes much longer than 10 minutes for largers system. We have a project in our research lab that takes somewhere around 3 hours to compile from start to finish. That being said, it does not mean that you have to recompile everything when you want to reconfigure a chip. Each chip can have a base set of logic, and have sectors where abstract "modules" can simply be "dropped in". While this can cause a performance hit, it is easy to implement new logic circuts for a device. FPGA's are also really starting to hit their stride and are growing by leaps and bounds.
Turing machines are not reconfigurable. They perform according to a fixed instruction set. The precursor to general-purpose, reconfigurable hardware is probably computers with microcoded instruction sets, such as the IBM 360 in 1964.
Intron: the portion of DNA which expresses nothing useful.
The FPU will be as good as you design it to be.
In comparison to custom built hardware an FPGA sucks, it's big, slow and power hungry. If you were to take a standard FPU and build it into an FPGA it would be useless.
But the whole point is that you don't need a general use FPU that can do everything. You only have one that can do the one specific operation that you need. e.g. If you need to add three 158 bit floating point numbers you have a bit of logic that can do that. It's 158 bits wide, has 3 inputs and one output. Who cares if it only runs at 1/10 of the clock speed of your 64bit cpu, it's still going to be faster.
Getting the system to be able to do that on the fly is the hard part, 99 times out of 100 it's probably quicker to do the work on a standard CPU than to work out how to configure the FPGA. But if you need to do the same operations over and over again then the advantages become huge.
As for the memory bandwidth issue, most large FPGAs include some fairly large amounts of RAM built into them. Certainly enough to do some basic data cacheing and queuing. It doesn't solve the problem but it helps.
Ah, the fame and fortune...
As a software design engineer at Nallatech, I'm pretty chuffed we came up on Slashdot.
Not wanting to come across as a pedant...
"software needed to run it, which is the key to the project, is vapourware"
This is not the case, with Nallatech's software is capable of providing the intercommunication (DIMEtalk), the low level control (FUSE) and the Algorithm implementation (double and single precision floating point cores, as well as a new tool, currently in beta, to simplify their use by developers).
"Nallatech, a company that makes software tools for FPGA programmers".
This is true, however we do equal amount of hardware and firmware development.
More info:
Read our white paper about supercomputing for the oil and gas industry, reg required I'm afraid?
The foot print of this thing could be tiny, as you can get 9 Virtex 2 pro FPGAs (Using BenBLUE-3 modules) on a BenERA Carrier card, and you can get 4 BenERAs into a cPCI rack, so to get 64 FPGAs you just need 2 standard cPCI racks. Since you can get 4 cPCI racks into you standard 19" server rack, which would kick out a massive 2 Teraflops.
Though, I can't help but think Cell processors might kick our asses, at least a little bit anyway. Sorry about all the links to Nallatech, just pointing folk to the info. Oh, by the way, I think the 1 Teraflop for 64 FPGAs is a very conservative estimate.